Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver SOIC 20

Data sheet acquired from Harris Semiconductor

SCHS192B

Features

• Buffered Inputs

• Three-State Outputs

• Applications in Multiple-Data-Bus Architecture

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC640, CD54HCT640

(CERDIP)

CD74HC640, CD74HCT640

(PDIP, SOIC)

TOP VIEW

Description

The ’HC640 and ’HCT640 silicon-gate CMOS three-state

bidirectional inverting and non-inverting buffers are intended

for two-way asynchronous communication between data

buses. They have high drive current outputs which enable

high-speed operation when driving large bus capacitances.

These circuits possess the low power dissipation of CMOS

circuits, and have speeds comparable to low power Schottky

TTL circuits. They can drive 15 LSTTL loads. The ’HC640

and ’HCT640 are inverting buffers.

The direction of data ﬂow (A to B, B to A) is controlled by the

DIR input.

Outputs are enabled by a low on the Output Enable input

(

OE); a high OE puts these devices in the high impedance

mode.

DIR

GND

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC640F3A -55 to 125 20 Ld CERDIP

CD54HCT640F3A -55 to 125 20 Ld CERDIP

CD74HC640E -55 to 125 20 Ld PDIP

CD74HC640M -55 to 125 20 Ld SOIC

CD74HCT640E -55 to 125 20 Ld PDIP

CD74HCT640M -55 to 125 20 Ld SOIC

January 1998 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC640, CD74HC640,

CD54HCT640, CD74HCT640

High-Speed CMOS Logic

Octal Three-State Bus Transceiver, Inverting

[ /Title

(CD74

HC640

CD74

HCT64

Sub-

ect

(High

Speed

CMOS

Summary of content (13 pages)

PAGE 1
[ /Title (CD74 HC640 , CD74 HCT64 0) /Subject (High Speed CMOS CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 Data sheet acquired from Harris Semiconductor SCHS192B January 1998 - Revised May 2003 High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting Features Description • Buffered Inputs The ’HC640 and ’HCT640 silicon-gate CMOS three-state bidirectional inverting and non-inverting buffers are intended for two-way asynchronous communication between data buses.
PAGE 2
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 Functional Diagram A0 B0 A1 THRU A6 B1 THRU B6 A7 B7 OE DIR OUTPUT ENABLE AND DIRECTION-SELECT LOGIC TRUTH TABLE CONTROL INPUTS DATA PORT STATUS OE DIR An Bn L L O I H H Z Z H L Z Z L H I O To prevent excess currents in the High-Z modes all I/O terminals should be terminated with 1kΩ to 1MΩ resistors.
PAGE 3
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 µA Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 6 - - ±0.5 - ±5 - ±10 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.
PAGE 5
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPHL, tPLH CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 90 - 115 - 135 ns 4.5 - - 18 - 23 - 27 ns CL = 15pF 5 - 7 - - - - - ns CL = 50pF 6 - - 15 - 20 - 23 ns CL = 50pF 2 - - 150 - 190 - 225 ns 4.
PAGE 6
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns 10% 2.7 1.3 OUTPUT LOW TO OFF 90% OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 9. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.