Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Differential SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS135F

Features

• True and Complementary Outputs

• Buffered Inputs and Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent

latches. Each one of the 2-bit latches is controlled by

separate Enable inputs (

1E and 2E) which are active LOW.

When the Enable input is HIGH data enters the latch and

appears at the Q output. When the Enable input (

1E and 2E)

is LOW the output is not affected.

Pinout

CD54HC75, CD54HCT75 (CERDIP)

CD74HC75 (PDIP, SOIC, SOP, TSSOP)

CD74HCT75 (PDIP, SOIC, TSSOP)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC75F3A -55 to 125 16 Ld CERDIP

CD54HCT75F3A -55 to 125 16 Ld CERDIP

CD74HC75E -55 to 125 16 Ld PDIP

CD74HC75M -55 to 125 16 Ld SOIC

CD74HC75MT -55 to 125 16 Ld SOIC

CD74HC75M96 -55 to 125 16 Ld SOIC

CD74HC75NSR -55 to 125 16 Ld SOP

CD74HC75PW -55 to 125 16 Ld TSSOP

CD74HC75PWR -55 to 125 16 Ld TSSOP

CD74HCT75E -55 to 125 16 Ld PDIP

CD74HCT75M -55 to 125 16 Ld SOIC

CD74HCT75PWT -55 to 125 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

1Q0

1D0

1D1

2D0

2Q1

2D1

1Q0

1Q1

GND

2Q0

2Q1

1Q1

March 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC75, CD74HC75,

CD54HCT75, CD74HCT75

Dual 2-Bit Bistable

Transparent Latch

[

/Title

(

CD74

C75,

D74

CT75

)

Sub-

ect

(

Dual

-Bit

istabl

Summary of content (19 pages)

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[ /Title (CD74 HC75, CD74 HCT75 ) /Subject (Dual 2-Bit Bistabl e CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Data sheet acquired from Harris Semiconductor SCHS135F Dual 2-Bit Bistable Transparent Latch March 1998 - Revised October 2003 Features Description • True and Complementary Outputs The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW.
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CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Functional Diagram 16 (10) 2 (6) Q0 1 (11) D0 1 OF 2 LATCHES 3 (7) D1 Q0 14 (8) Q1 15 (9) Q1 13 (4) E TRUTH TABLE INPUTS OUTPUTS D E Q Q L H L H H H H L X L Q0 Q0 H= High Level L= Low Level X= Don’t Care Q0 = The level of Q before the transition of E. Logic Diagram LATCH 0 16 (10) 2 (6) D0 D Q LE LE Q0 1 (11) Q0 13 (4) E LE 14 (8) Q Q1 LE LE D Q 3 (7) D1 P P N N LE 15 (9) Q1 LE Q LATCH 1 5 12 VCC GND FIGURE 1.
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CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .
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CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 4 - 40 - 80 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL - 0.
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CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Prerequisite For Switching Specifications PARAMETER Hold Time Enable to D (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tH - 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns HCT TYPES Pulse Width Enable Input tW - 4.5 16 - - 20 - 24 - ns Setup Time D to Enable tSU - 4.5 12 - - 15 - 18 - ns Hold Time Enable to D tH - 4.
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CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Propagation Delay, Enable to Q tPLH, tPHL CL = 50pF 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns Output Transition Time tTLH, tTHL CL = 50pF 4.
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CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC75M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC75PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC75PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC75M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC75PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC75PWT TSSOP PW 16 250 367.0 367.0 35.
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