Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS137D
Features
• Typical Propagation Delay: 9ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Applications
• Logical Comparators
• Parity Generators and Checkers
• Adders and Subtractors
Description
The ’HC86 and ’HCT86 contain four independent
EXCLUSIVE OR gates in one package. They provide the
system designer with a means for implementation of the
EXCLUSIVE OR function. Logic gates utilize silicon gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
Pinout
CD54HC86, CD54HCT86
(CERDIP)
CD74HC86, CD74HCT86
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC86F3A -55 to 125 14 Ld CERDIP
CD54HCT86F3A -55 to 125 14 Ld CERDIP
CD74HC86E -55 to 125 14 Ld PDIP
CD74HC86M -55 to 125 14 Ld SOIC
CD74HC86MT -55 to 125 14 Ld SOIC
CD74HC86M96 -55 to 125 14 Ld SOIC
CD74HCT86E -55 to 125 14 Ld PDIP
CD74HCT86M -55 to 125 14 Ld SOIC
CD74HCT86MT -55 to 125 14 Ld SOIC
CD74HCT86M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
August 1997 - Revised September 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC86, CD74HC86,
CD54HCT86, CD74HCT86
High-Speed CMOS Logic
Quad 2-Input EXCLUSIVE-OR Gate
[
/Title
(
CD74
H
C86,
C
D74
H
CT86
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
Q
uad
2
-Input
E
XCL
U
SIVE
O
R