Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS126D
Features
• Buffered Inputs
• Typical Propagation Delay: 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Output Pull-up to 10V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally as well as
pin compatible with the standard LS logic family.
These open drain NAND gates can drive into resistive loads
to output voltages as high as 10V. Minimum values of R
L
required versus load voltage are shown in Figure 2.
Pinout
CD54HC03, CD54HCT03
(CERDIP)
CD74HC03, CD74HCT03
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC03F3A -55 to 125 14 Ld CERDIP
CD54HCT03F3A -55 to 125 14 Ld CERDIP
CD74HC03E -55 to 125 14 Ld PDIP
CD74HC03M -55 to 125 14 Ld SOIC
CD74HC03MT -55 to 125 14 Ld SOIC
CD74HC03M96 -55 to 125 14 Ld SOIC
CD74HCT03E -55 to 125 14 Ld PDIP
CD74HCT03M -55 to 125 14 Ld SOIC
CD74HCT03MT -55 to 125 14 Ld SOIC
CD74HCT03M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
February 1998 - Revised September 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC03, CD74HC03,
CD54HCT03, CD74HCT03
High-Speed CMOS Logic
Quad 2-Input NAND Gate with Open Drain
[
/Title
(
CD74H
C
03,
C
D74H
C
T03)
/
Subject
(
High
S
peed
C
MOS
L
ogic
Q
uad 2-
I
nput