Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS145E
Features
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
• Typical Propagation Delay: 10ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 37%, N
IH
= 51% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC132 and ’HCT132 each contain four 2-input NAND
Schmitt Triggers in one package. This logic device utilizes
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The HCT logic family is
functionally pin compatible with the standard LS logic family.
Pinout
CD54HC132, CD54HCT132
(CERDIP)
CD74HC132, CD74HCT132
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC132F3A -55 to 125 14 Ld CERDIP
CD54HCT132F3A -55 to 125 14 Ld CERDIP
CD74HC132E -55 to 125 14 Ld PDIP
CD74HC132M -55 to 125 14 Ld SOIC
CD74HC132MT -55 to 125 14 Ld SOIC
CD74HC132M96 -55 to 125 14 Ld SOIC
CD74HCT132E -55 to 125 14 Ld PDIP
CD74HCT132M -55 to 125 14 Ld SOIC
CD74HCT132MT -55 to 125 14 Ld SOIC
CD74HCT132M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
August 1997 - Revised March 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
CD54HC132, CD74HC132,
CD54HCT132, CD74HCT132
High-Speed CMOS Logic
Quad 2-Input NAND Schmitt Trigger
[
/Title
(
CD74
H
C132
,
C
D74
H
CT13
2
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
Q
uad
2
-Input
N
AND
S
chmit