Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Demultiplexer, decoder Decoder/demultiplexer Single supply SOIC 24

Data sheet acquired from Harris Semiconductor

SCHS152D

Features

• Two Enable Inputs to Facilitate Demultiplexing and

Cascading Functions

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30%of V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC154 and ’HCT154 are 4- to 16-line

decoders/demultiplexers with two enable inputs, E1 and E2.

A High on either enable input forces the output into the High

state. The demultiplexing function is performed by using the

four input lines, A0 to A3, to select the output lines

Y0 to

Y15, and using one enable as the data input while holding

the other enable low.

Pinout

CD54HC154, CD54HCT154

(CERDIP)

CD74HC154, CD74HCT154

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC154F3A -55 to 125 24 Ld CERDIP

CD54HCT154F3A -55 to 125 24 Ld CERDIP

CD74HC154E -55 to 125 24 Ld PDIP

CD74HC154EN -55 to 125 24 Ld PDIP

CD74HC154M -55 to 125 24 Ld SOIC

CD74HC154M96 -55 to 125 24 Ld SOIC

CD74HCT154E -55 to 125 24 Ld PDIP

CD74HCT154EN -55 to 125 24 Ld PDIP

CD74HCT154M -55 to 125 24 Ld SOIC

CD74HCT154M96 -55 to 125 24 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

Y10

GND

Y15

Y13

Y12

Y11

Y14

September 1997 - Revised June 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC154, CD74HC154,

CD54HCT154, CD74HCT154

High-Speed CMOS Logic

4- to 16-Line Decoder/Demultiplexer

[

/Title

(

CD74

C154

D74

CT15

)

Sub-

ect

(

High

peed

MOS

ogic

-to-16

ine

ecod

r/Dem

Summary of content (17 pages)

PAGE 1
[ /Title (CD74 HC154 , CD74 HCT15 4) /Subject (High Speed CMOS Logic 4-to-16 Line Decod er/Dem CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 Data sheet acquired from Harris Semiconductor SCHS152D High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer September 1997 - Revised June 2004 Features A High on either enable input forces the output into the High state.
PAGE 2
CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 Functional Diagram 1 2 3 4 5 6 7 A0 23 8 A1 22 9 A2 A3 21 10 20 11 13 14 15 E1 E2 18 16 19 17 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 GND = 12 VCC = 24 TRUTH TABLE INPUTS OUTPUTS E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 L L L L L L L H H H H H H H H H H H H H H H L L L L L H H L H H H H H H H H H H H H H H L L L L H L H H L H H
PAGE 3
CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
PAGE 4
CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
PAGE 5
CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 Switching Specifications Input tr, tf = 6ns PARAMETER E1 to Output E2 to Output Output Transition Time (Figure 1) (Continued) TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns tPLH, tPHL CL = 50pF 2 - - 175 - 220 - 265 ns 4.
PAGE 6
Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC154M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CD74HC154M96G4 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CD74HCT154M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC154M96 SOIC DW 24 2000 366.0 364.0 50.0 CD74HC154M96G4 SOIC DW 24 2000 367.0 367.0 45.0 CD74HCT154M96 SOIC DW 24 2000 367.0 367.0 45.
PAGE 12
MECHANICAL DATA MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997 J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN B 13 24 C 1 12 0.065 (1,65) 0.045 (1,14) Lens Protrusion (Lens Optional) 0.010 (0.25) MAX 0.175 (4,45) 0.140 (3,56) 0.090 (2,29) 0.060 (1,53) A Seating Plane 0.018 (0,46) MIN 24 PINS ** DIM ”A” ”B” ”C” NARR 0.125 (3,18) MIN 0.022 (0,56) 0.014 (0,36) 0.100 (2,54) 0.012 (0,30) 0.008 (0,20) 28 WIDE NARR 40 32 WIDE NARR WIDE NARR WIDE MAX 0.624(15,85) 0.
PAGE 13
PAGE 14
MECHANICAL DATA MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002 N (R–PDIP–T24) PLASTIC DUAL–IN–LINE 1.222 (31,04) MAX 24 13 0.360 (9,14) MAX 1 12 0.070 (1,78) MAX 0.200 (5,08) MAX 0.425 (10,80) MAX 0.020 (0,51) MIN Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0’–15’ 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) NOM 4040051–3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C.
PAGE 15
PAGE 16
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.