Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HCT Negative slope 20 MHz SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS154D

The CD54HCT161 is obsolete

and no longer is supplied.

Features

• ’HC161, ’HCT161 4-Bit Binary Counter,

Asynchronous Reset

• ’HC163, ’HCT163 4-Bit Binary Counter,

Synchronous Reset

• Synchronous Counting and Loading

• Two Count Enable Inputs for n-Bit Cascading

• Look-Ahead Carry for High-Speed Counting

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC161, ’HCT161, ’HC163, and ’HCT163 are

presettable synchronous counters that feature look-ahead

carry logic for use in high-speed counting applications. The

’HC161 and ’HCT161 are asynchronous reset decade and

binary counters, respectively; the ’HC163 and ’HCT163

devices are decade and binary counters, respectively, that

are reset synchronously with the clock. Counting and

parallel presetting are both accomplished synchronously

with the negative-to-positive transition of the clock.

A low level on the synchronous parallel enable input, SPE,

disables counting operation and allows data at the P0 to P3

inputs to be loaded into the counter (provided that the

setup and hold requirements for SPE are met).

All counters are reset with a low level on the Master Reset

input, MR. In the ’HC163 and ’HCT163 counters

(synchronous reset types), the requirements for setup and

hold time with respect to the clock must be met.

Two count enables, PE and TE, in each counter are

provided for n-bit cascading. In all counters reset action

occurs regardless of the level of the

SPE, PE and TE inputs

(and the clock input, CP, in the ’HC161 and ’HCT161

types).

If a decade counter is preset to an illegal state or assumes

an illegal state when power is applied, it will return to the

normal sequence in one count as shown in state diagram.

The look-ahead carry feature simplifies serial cascading of

the counters. Both count enable inputs (PE and TE) must

be high to count. The TE input is gated with the Q outputs

of all four stages so that at the maximum count the terminal

count (TC) output goes high for one clock period. This TC

pulse is used to enable the next cascaded stage.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC161F3A -55 to 125 16 Ld CERDIP

CD54HC163F3A -55 to 125 16 Ld CERDIP

CD54HCT163F3A -55 to 125 16 Ld CERDIP

CD74HC161E -55 to 125 16 Ld PDIP

CD74HC161M -55 to 125 16 Ld SOIC

CD74HC161MT -55 to 125 16 Ld SOIC

CD74HC161M96 -55 to 125 16 Ld SOIC

CD74HC163E -55 to 125 16 Ld PDIP

CD74HC163M -55 to 125 16 Ld SOIC

CD74HC163MT -55 to 125 16 Ld SOIC

CD74HC163M96 -55 to 125 16 Ld SOIC

CD74HCT161E -55 to 125 16 Ld PDIP

CD74HCT161M -55 to 125 16 Ld SOIC

CD74HCT161MT -55 to 125 16 Ld SOIC

CD74HCT161M96 -55 to 125 16 Ld SOIC

CD74HCT163E -55 to 125 16 Ld PDIP

CD74HCT163M -55 to 125 16 Ld SOIC

CD74HCT163MT -55 to 125 16 Ld SOIC

CD74HCT163M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96

denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC161, CD54/74HCT161,

CD54/74HC163, CD54/74HCT163

High-Speed CMOS Logic

Presettable Counters

[ /Title

(CD74

HC161

D74

HCT16

CD74

HC163

D74

HCT16

/Sub-

ject

(High

Speed

CMOS

Logic

Preset-

table

Counte

rs)

/Autho

r ()

/Key-

words

(High

Speed

CMOS

Logic

Preset-

table

Counte

rs,

High

Speed

Summary of content (20 pages)

PAGE 1
[ /Title (CD74 HC161 , CD74 HCT16 1, CD74 HC163 , CD74 HCT16 3) /Subject (High Speed CMOS Logic Presettable Counte rs) /Autho r () /Keywords (High Speed CMOS Logic Presettable Counte rs, High Speed The CD54HCT161 is obsolete and no longer is supplied.
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Pinout CD54HC161, CD54HCT161, CD54HC163, CD54HCT163 (CERDIP) CD74HC161, CD74HCT161, CD74HC163, CD74HCT163 (PDIP, SOIC) TOP VIEW MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE 9 SPE GND 8 Functional Diagram P0 3 SPE CP MR PE TE P1 4 P2 5 P3 6 9 14 2 13 1 12 7 11 10 15 2 Q0 Q1 Q2 Q3 TC
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161 INPUTS OPERATING MODE OUTPUTS MR CP PE TE SPE Pn Qn TC Reset (Clear) L X X X X X L L Parallel Load H ↑ X X l l L L H ↑ X X l h H (Note 1) Count H ↑ h h h (Note 3) X Count (Note 1) Inhibit H X I (Note 2) X h (Note 3) X qn (Note 1) H X X I (Note 2) h (Note 3) X qn L MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163 INPUTS OPERATING MODE
PAGE 4
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . .
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS fMAX - 2 6 - - 5 - 4 - MHz 4.5 30 - - 24 - 20 - MHz 6 35 - - 28 - 24 - MHz 2 80 - - 100 - 120 - ns 4.
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Maximum CP Frequency fMAX - 4.5 30 - - 24 - 20 - MHz CP Width (Low) (Note 6) tW(L) - 4.5 16 - - 20 - 24 - ns MR Pulse Width (161) tW - 4.5 20 - - 25 - 30 - ns Setup Time, Pn to CP tSU - 4.
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC PARAMETER MR to Qn (161) MR to TC (161) Output Transition Time -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPHL CL = 50pF 2 - - 210 - 265 - 315 ns 4.
PAGE 9
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Timing Diagram MASTER RESET (161) (ASYNCHRONOUS) MASTER RESET (163) (SYNCHRONOUS) SPE P0 PRESET DATA INPUTS P1 P2 P3 CP (161) CP (163) COUNT ENABLES PE TE Q0 Q1 OUTPUTS Q2 Q3 TC 12 RESET 13 14 15 0 COUNT PRESET Sequence illustrated on waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit.
PAGE 10
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 1.3V 10% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 90% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC161M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC163M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT161M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC161M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC163M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT161M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT163M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.