Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS160C
Features
• Common Clock and Asynchronous Reset on Four
D-Type Flip-Flops
• Positive Edge Pulse Triggering
• Complementary Outputs
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC175 and ’HCT175 are high speed Quad D-type Flip-
Flops with individual D-inputs and Q,
Q complementary
outputs. The devices are fabricated using silicon gate CMOS
technology. They have the low power consumption
advantage of standard CMOS ICs and the ability to drive 10
LSTTL devices.
Information at the D input is transferred to the Q,
Q outputs on
the positive going edge of the clock pulse. All four Flip-Flops
are controlled by a common clock (CP) and a common reset
(
MR). Resetting is accomplished by a low voltage level
independent of the clock. All four Q outputs are reset to a
logic 0 and all four
Q outputs to a logic 1.
Pinout
CD54HC175, CD54HCT175
(CERDIP)
CD74HC175, CD74HCT175
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC175F3A -55 to 125 16 Ld CERDIP
CD54HCT175F3A -55 to 125 16 Ld CERDIP
CD74HC175E -55 to 125 16 Ld PDIP
CD74HC175M -55 to 125 16 Ld SOIC
CD74HC175MT -55 to 125 16 Ld SOIC
CD74HC175M96 -55 to 125 16 Ld SOIC
CD74HCT175E -55 to 125 16 Ld PDIP
CD74HCT175M -55 to 125 16 Ld SOIC
CD74HCT175MT -55 to 125 16 Ld SOIC
CD74HCT175M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
MR
Q
0
Q
0
D
0
D
1
Q
1
GND
V
CC
Q
3
Q
3
D
3
D
2
Q
2
Q
2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CP
Q
1
August 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC175, CD74HC175,
CD54HCT175, CD74HCT175
High-Speed CMOS Logic
Quad D-Type Flip-Flop with Reset
[
/Title
(
CD74
H
C175
,
C
D74
H
CT17
5
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
Q
uad
D
-
T
ype
F
lip-