Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HCT SOIC 14

Data sheet acquired from Harris Semiconductor

SCHS130C

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V

= 5V,

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOS

technology to achieve operating speeds similar to LSTTL

gates with the low power consumption of standard CMOS

integrated circuits. All devices have the ability to drive 10

LSTTL loads. The HCT logic family is functionally pin

compatible with the standard LS logic family.

Pinout

CD54HC20, CD54HCT20

(CERDIP)

CD74HC20, CD74HCT20

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC20F3A -55 to 125 14 Ld CERDIP

CD54HCT20F3A -55 to 125 14 Ld CERDIP

CD74HC20E -55 to 125 14 Ld PDIP

CD74HC20M -55 to 125 14 Ld SOIC

CD74HC20MT -55 to 125 14 Ld SOIC

CD74HC20M96 -55 to 125 14 Ld SOIC

CD74HCT20E -55 to 125 14 Ld PDIP

CD74HCT20M -55 to 125 14 Ld SOIC

CD74HCT20MT -55 to 125 14 Ld SOIC

CD74HCT20M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

The sufﬁx T denotes a small-quantity reel

of 250.

GND

August 1997 - Revised September 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC20, CD74HC20,

CD54HCT20, CD74HCT20

High-Speed CMOS Logic

Dual 4-Input NAND Gate

[

/Title

(

CD74H

20,

D74H

T20)

Subject

(

High

peed

MOS

ogic

ual 4-

nput

Summary of content (14 pages)

PAGE 1
[ /Title (CD74H C20, CD74H CT20) /Subject (High Speed CMOS Logic Dual 4Input CD54HC20, CD74HC20, CD54HCT20, CD74HCT20 Data sheet acquired from Harris Semiconductor SCHS130C High-Speed CMOS Logic Dual 4-Input NAND Gate August 1997 - Revised September 2003 Features Description • Buffered Inputs The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits.
PAGE 2
CD54HC20, CD74HC20, CD54HCT20, CD74HCT20 Functional Diagram 1A 1B NC 1C 1D 1Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2D 2C NC 2B 2A 2Y TRUTH TABLE INPUTS OUTPUT nA nB nC nD nY L X X X H X L X X H X X L X H X X X L H H H H H L H = High Voltage Level, L = Low Voltage Level, X = Irrelevant HC Logic Symbol HCT Logic Symbol nA nA nB nY nB nC nD nY nC nD 2
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CD54HC20, CD74HC20, CD54HCT20, CD74HCT20 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . .
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CD54HC20, CD74HC20, CD54HCT20, CD74HCT20 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 2 - 20 - 40 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.
PAGE 5
CD54HC20, CD74HC20, CD54HCT20, CD74HCT20 Switching Specifications Input tr, tf = 6ns PARAMETER Transition Times (Figure1) Input Capacitance Power Dissipation Capacitance (Notes 3, 4) (Continued) SYMBOL TEST CONDITIONS tTLH, tTHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 75 - 95 - 110 ns 4.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC20M96 SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC20MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT20M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC20M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC20MT SOIC D 14 250 367.0 367.0 38.0 CD74HCT20M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HCT20MT SOIC D 14 250 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.