Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver SOIC 20

Data sheet acquired from Harris Semiconductor

SCHS119A

Features

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay (A to B, B to A) 9ns at V

= 5V, C

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC245, CD54HCT245

(CERDIP)

CD74HC245, CD74HCT245

(PDIP, SOIC)

TOP VIEW

Description

The CD54HC245, CD54HCT245, and CD74HC245,

CD74HCT245 are high-speed octal three-state bidirectional

transceivers intended for two-way asynchronous

communication between data buses. They have high drive

current outputs which enable high-speed operation while

driving large bus capacitances. They provide the low power

consumption of standard CMOS circuits with speeds and

drive capabilities comparable to that of LSTTL circuits.

The CD54HC245, CD54HCT245, CD74HC245 and

CD74HCT245 allow data transmission of the B bus or from

the B bus to the A bus. The logic level at the direction input

(DIR) determines the direction. The output enable input

(

OE), when high, puts the I/O ports in the high-impedance

state.

The HC/HCT245 is similar in operation to the HC/HCT640

and the HC/HCT643.

DIR

GND

Ordering Information

PART NUMBER

TEMP.

RANGE (

C) PACKAGE

CD54HC245F3A -55 to 125 20 Ld CERDIP

CD54HCT245F3A -55 to 125 20 Ld CERDIP

CD74HC245E -55 to 125 20 Ld PDIP

CD74HC245M -55 to 125 20 Ld SOIC

CD74HC245M96 -55 to 125 20 Ld SOIC

CD74HCT245E -55 to 125 20 Ld PDIP

CD74HCT245M -55 to 125 20 Ld SOIC

CD74HCT245M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC245, CD74HC245,

CD54HCT245, CD74HCT245

High-Speed CMOS Logic Octal-Bus Transceiver,

Three-State, Non-Inverting

[ /Title

(CD54

HC245

CD54

HCT24

CD74

HC245

CD74

HCT24

Sub-

ect

(High

Speed

November 1997 - Revised May 2003

Summary of content (15 pages)

PAGE 1
[ /Title (CD54 HC245 , CD54 HCT24 5, CD74 HC245 , CD74 HCT24 5) /Subject (High Speed CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Data sheet acquired from Harris Semiconductor SCHS119A November 1997 - Revised May 2003 High-Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting Features Description • Buffered Inputs The CD54HC245, CD54HCT245, and CD74HC245, CD74HCT245 are high-speed octal three-state bidirectional transceivers intended for two-way asynchronous communication between data bu
PAGE 2
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Functional Diagram A0 A1 A2 A3 A4 A5 A6 A7 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 1 DIR OE 19 TRUTH TABLE CONTROL INPUTS OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Level, L = Low Level, X = Irrelevant To prevent excess currents in the High-Z (Isolation) modes all I/O terminals should be terminated with 10kΩ to 1MΩ resistors.
PAGE 3
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS PARAMETER SYMBOL VI (V) IO (mA) Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 6 - - ±0.5 - ±5 - ±10 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.
PAGE 5
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPHL, tPLH CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 110 - 140 - 165 ns 4.5 - - 22 - 28 - 33 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 19 - 24 - 28 ns CL = 50pF 2 - - 150 - 190 - 225 ns 4.
PAGE 6
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns tr VCC 90% 10% OUTPUTS ENABLED tPZH OUTPUT HIGH TO OFF FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ 50% 3V tPZL tPLZ 90% OUTPUTS DISABLED 6ns 2.7 1.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC245M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT245M96 SOIC DW 20 2000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.