Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HCT Negative slope 30 MHz PDIP 16

Data sheet acquired from Harris Semiconductor

SCHS207G

Features

• Onboard Oscillator

• Common Reset

• Negative-Edge Clocking

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC4060 and ’HCT4060 each consist of an oscillator

section and 14 ripple-carry binary counter stages. The

oscillator conﬁguration allows design of either RC or crystal

oscillator circuits. A Master Reset input is provided which

resets the counter to the all-0’s state and disables the

oscillator. A high level on the MR line accomplishes the reset

function. All counter stages are master-slave ﬂip-ﬂops. The

state of the counter is advanced one step in binary order on

the negative transition of φI (and φO). All inputs and outputs

are buffered. Schmitt trigger action on the input-pulse-line

permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator

section the HCT4060 input pulse switch points are the same

as in the HC4060; only the MR input in the HCT4060 has

TTL switching levels.

Pinout

CD54HC4060, CD54HCT4060 (CERDIP)

CD74HC4060 (PDIP, SOIC, TSSOP)

CD74HCT4060 (PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4060F3A -55 to 125 16 Ld CERDIP

CD54HCT4060F3A -55 to 125 16 Ld CERDIP

CD74HC4060E -55 to 125 16 Ld PDIP

CD74HC4060M -55 to 125 16 Ld SOIC

CD74HC4060MT -55 to 125 16 Ld SOIC

CD74HC4060M96 -55 to 125 16 Ld SOIC

CD74HC4060PW -55 to 125 16 Ld TSSOP

CD74HC4060PWR -55 to 125 16 Ld TSSOP

CD74HC4060PWT -55 to 125 16 Ld TSSOP

CD74HCT4060E -55 to 125 16 Ld PDIP

CD74HCT4060M -55 to 125 16 Ld SOIC

CD74HCT4060MT -55 to 125 16 Ld SOIC

CD74HCT4060M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

Q12

Q13

Q14

GND

φI

φO

Q10

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4060, CD74HC4060,

CD54HCT4060, CD74HCT4060

High-Speed CMOS Logic

14-Stage Binary Counter with Oscillator

[

/Title

(

CD74

C406

D74

CT40

Sub-

ect

(

High

peed

MOS

Summary of content (21 pages)

PAGE 1
[ /Title (CD74 HC406 0, CD74 HCT40 60) /Subject (High Speed CMOS CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 Data sheet acquired from Harris Semiconductor SCHS207G High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator February 1998 - Revised October 2003 the negative transition of φI (and φO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
PAGE 2
CD54/74HC4060, CD54/74HCT4060 Functional Diagram 7 Q4 5 Q5 4 12 Q6 MR 6 Q7 φI 14 14-STAGE RIPPLE COUNTER AND OSCILLATOR 11 Q8 13 Q9 15 Q10 1 Q12 2 Q13 3 Q14 φO φO øO øO ø1 9 GND = 8 VCC = 16 10 9 ø1 ø4 Q1 FF1 11 ø1 FF4 ø4 Q1 R MR ø5 Q4 ø14 Q13 Q14 10 FF5 - FF13 ø5 Q4 R FF14 ø14 Q13 Q14 R R 12 7 2 Q4 5, 4, 6, 14, 13, 15, 1 Q13 Q5 - Q10, Q12 FIGURE 1.
PAGE 3
CD54/74HC4060, CD54/74HCT4060 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54/74HC4060, CD54/74HCT4060 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) High-Level Output Voltage φO Output (Pin 10) TTL Loads (Note 2) VOH VCC or GND -2.6 4.5 3.98 - - 3.84 - 3.7 - V -3.3 6 5.48 - - 5.34 - 5.2 - V Low-Level Output Voltage φO Output (Pin 10) CMOS Loads VOL VCC or GND 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.
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CD54/74HC4060, CD54/74HCT4060 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) Low-Level Output Voltage φO Output (Pin 10) TTL Loads VOL VCC or GND 2.6 4.5 - - 0.26 - 0.33 - 0.4 V High-Level Output Voltage φO Output (Pin 9) TTL Loads VOH VIL or VIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V Low-Level Output Voltage φO Output (Pin 9) TTL Loads VOL VIH or VIL (Note 3) 3.2 4.5 - 0.26 - 0.33 - 0.
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CD54/74HC4060, CD54/74HCT4060 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns HCT TYPES Maximum Input, Pulse Frequency fmax 4.5 30 - - 25 - - 20 - - MHz Input Pulse Width tW 4.5 16 - - 20 - - 24 - - ns tREM 4.
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CD54/74HC4060, CD54/74HCT4060 Switching Specifications PARAMETER Qn to Qn+1 Input tr, tf = 6ns (Continued) -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - - - - - - ns 4.5 - - 16 - 20 - 24 ns CL = 15pF 5 - 6 - - - - - ns CL = 50pF 6 - - - - - - - ns CL = 50pF 2 - - - - - - - ns 4.
PAGE 8
CD54/74HC4060, CD54/74HCT4060 Typical Performance Curves tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL 50% CLOCK 50% 1.3V 0.3V tWH tf = 6ns GND tTLH 3V 2.7V 1.3V 0.3V INPUT GND tTHL 90% 50% 10% INVERTING OUTPUT GND tr = 6ns VCC tTHL 1.3V FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns 90% 50% 10% I fCL NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4060M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4060PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4060PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4060M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4060PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4060PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT4060M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.