Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS133C
Features
• Buffered Inputs and Outputs
• Typical Propagation Delay: 12ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL decoders with the low power
consumption of standard CMOS integrated circuits. These
devices have the capability of driving 10 LSTLL loads and
are compatible with the standard LS logic family. One of ten
outputs (low on select) is selected in accordance with the
BCD input. Non-valid BCD inputs result in none of the
outputs being selected (all outputs are high).
Pinout
CD54HC42
(CERDIP)
CD74HC42
(PDIP, SOIC)
CD74HCT42
(PDIP)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (
o
C) PACKAGE
CD54HC42F3A -55 to 125 16 Ld CERDIP
CD74HC42E -55 to 125 16 Ld PDIP
CD74HC42M -55 to 125 16 Ld SOIC
CD74HCT42E -55 to 125 16 Ld PDIP
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Y0
Y1
Y2
Y3
Y4
Y5
GND
Y6
V
CC
A1
A2
A3
Y9
Y8
Y7
A0
August 1997 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003 Texas Instruments Incorporated.
CD54HC42, CD74HC42,
CD74HCT42
High-Speed CMOS Logic
BCD-to-Decimal Decoders (1 of 10)
[ /Title
(CD74H
C42,
CD74H
CT42)
/
Subject
(High
Speed
CMOS
Logic
BCD To
Deci-