Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HCT Positive, Negtive 25 MHz PDIP 16

Data sheet acquired from Harris Semiconductor

SCHS216D

Features

• Positive or Negative Edge Triggering

• Synchronous Internal Carry Propagation

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The CD74HC4518 is a dual BCD up-counter. The ’HC4520

and CD74HCT4520 are dual binary up-counters. Each

device consists of two independent internally synchronous

4-stage counters. The counter stages are D-type ﬂip-ﬂops

having interchangeable CLOCK and ENABLE lines for

incrementing on either the positive-going or the negative-

going transition of CLOCK. The counters are cleared by high

levels on the MASTER RESET lines. The counter can be

cascaded in the ripple mode by connecting Q

to the

ENABLE input of the subsequent counter while the CLOCK

input of the latter is held low.

Pinout

CD54HC4520

(CERDIP)

CD74HC4518

(PDIP)

CD74HC4520, CD74HCT4520,

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4520F3A -55 to 125 16 Ld CERDIP

CD74HC4518E -55 to 125 16 Ld PDIP

CD74HC4520E -55 to 125 16 Ld PDIP

CD74HC4520M -55 to 125 16 Ld SOIC

CD74HC4520MT -55 to 125 16 Ld SOIC

CD74HC4520M96 -55 to 125 16 Ld SOIC

CD74HCT4520E -55 to 125 16 Ld PDIP

CD74HCT4520M -55 to 125 16 Ld SOIC

CD74HCT4520MT -55 to 125 16 Ld SOIC

CD74HCT4520M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

1CP

GND

1MR

2CP

2MR

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD74HC4518, CD54HC4520,

CD74HC4520, CD74HCT4520

High-Speed CMOS Logic

Dual Synchronous Counters

[

/Title

(

CD74

C451

D74

C452

D74

CT45

Sub-

ect

Summary of content (17 pages)

PAGE 1
[ /Title (CD74 HC451 8, CD74 HC452 0, CD74 HCT45 20) /Subject CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Data sheet acquired from Harris Semiconductor SCHS216D High-Speed CMOS Logic Dual Synchronous Counters November 1997 - Revised October 2003 Features having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negativegoing transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines.
PAGE 2
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Functional Diagram 1CP 1E ÷10/÷16 1 2CP 2E 1Q1 2 CL 5 1Q2 6 1Q3 7 ÷10/÷16 9 11 2Q0 12 2Q1 10 CL 13 2Q2 R 2MR 1Q0 4 R 1MR 3 14 2Q3 GND = 8 VCC = 16 15 TRUTH TABLE CP E MR OUTPUT STATE ↑ H L Increment Counter L ↓ L Increment Counter ↓ X L No Change X ↑ L No Change ↑ L L No Change H ↓ L No Change X X H Q0 thru Q3 = L H = High State. L = Low State. ↑ = High-to-Low Transition.
PAGE 3
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . .
PAGE 4
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -55oC TO 125oC -40oC TO 85oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.
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CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Set-up Time, Enable to CP Removal Time, MR to CP Set-up Time, CP to Enable Removal Time, MR to Enable -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tSU 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 0 - - 0 - 0 - ns 4.
PAGE 6
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Switching Specifications Input tr, tf = 6ns (Continued) TEST SYMBOL CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 53 - 66 - 80 ns HCT TYPES Propagation Delay CP to Qn tPLH, tPHL CL = 50pF CL = 15pF 5 - 22 - - - - - ns CL = 50pF 4.
PAGE 7
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 90% INVERTING OUTPUT tPHL FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 1.3V 10% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.7V 1.3V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4520M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT4520M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4520M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT4520M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.