Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state PDIP 20

Data sheet acquired from Harris Semiconductor

SCHS187C

Features

• Common Latch-Enable Control

• Common Three-State Output Enable Control

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capacity

• Typical Propagation Delay = 13ns at V

= 5V,

= 15pF, T

= 25

C (Data to Output)

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are

high-speed Octal Transparent Latches manufactured with

silicon gate CMOS technology. They possess the low power

consumption of standard CMOS integrated circuits, as well as

the ability to drive 15 LSTTL devices.

The outputs are transparent to the inputs when the latch

enable (

LE) is high. When the latch enable (LE) goes low the

data is latched. The output enable (OE) controls the

three-state outputs. When the output enable (OE) is high the

outputs are in the high impedance state. The latch operation

is independent of the state of the output enable.

The ’HC533 and ’HCT533 are identical in function to the

’HC563 and CD74HCT563 but have different pinouts. The

’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;

the latter are non-inverting types.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC533F3A -55 to 125 20 Ld CERDIP

CD54HC563F3A -55 to 125 20 Ld CERDIP

CD54HCT533F3A -55 to 125 20 Ld CERDIP

CD74HC533E -55 to 125 20 Ld PDIP

CD74HC563E -55 to 125 20 Ld PDIP

CD74HC563M -55 to 125 20 Ld SOIC

CD74HCT533E -55 to 125 20 Ld PDIP

CD74HCT563E -55 to 125 20 Ld PDIP

CD74HCT563M -55 to 125 20 Ld SOIC

January 1998 - Revised July 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC533, CD54/74HCT533,

CD54/74HC563, CD74HCT563

High-Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

[ /Title

(CD74H

C533,

CD74H

CT533,

CD74H

C563,

CD74H

CT563)

/Subject

(High

Speed

Summary of content (16 pages)

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[ /Title (CD74H C533, CD74H CT533, CD74H C563, CD74H CT563) /Subject (High Speed CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Data sheet acquired from Harris Semiconductor SCHS187C January 1998 - Revised July 2003 High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs Features Description • Common Latch-Enable Control The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high-speed Octal Transparent Latches manufactured with silicon gate CMOS technology.
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Pinouts CD54HC533, CD54HCT533 (CERDIP) CD74HC533, CD74HCT533 (PDIP) TOP VIEW CD54HC563 (CERDIP) CD74HC563, CD74HCT563 (PDIP, SOIC) TOP VIEW OE 1 20 VCC OE 1 Q0 2 19 Q7 D0 2 19 Q0 D0 3 18 D7 D1 3 18 Q1 20 VCC D1 4 17 D6 D2 4 17 Q2 Q1 5 16 Q6 D3 5 16 Q3 Q2 6 15 Q5 D4 6 15 Q4 D2 7 14 D5 D5 7 14 Q5 D3 8 13 D4 D6 8 13 Q6 Q3 9 12 Q4 D7 9 12 Q7 GND 10 11 LE GND 10 11 LE Functional Block Diagram HC/HCT533 D0 D1 D O D
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . .
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC SYMBOL VI (V) IO (mA) VCC (V) - VIL or VIH VO = VCC or GND High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Three-State Leakage Current -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.5 - ±5 - ±10 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 35 - - 45 - 55 - ns 4.
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Switching Specifications PARAMETER Enable Times (HC533) Disable Times (HC533) Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPZH, tPZL CL = 50pF tPHZ, tPLZ tPZH, tPZL, tPHZ, tPLZ VCC (V) -40oC TO 85oC -55oC TO 125oC TYP MAX MAX MAX UNITS 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 150 190 225 ns 4.
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 1.3V 10% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.
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CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE tr VCC 90% 50% 10% OUTPUTS ENABLED OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf 2.7 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.