Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 20

Data sheet acquired from Harris Semiconductor

SCHS189C

Features

• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

• ’HC541, ’HCT541 . . . . . . . . . . . . . . . . . . . . . . Non-Inverting

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay = 9ns at V

= 5V,

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC540 and CD74HCT540 are Inverting Octal Buffers

and Line Drivers with Three-State Outputs and the capability

to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non-

Inverting Octal Buffers and Line Drivers with Three-State Out-

puts that can drive 15 LSTTL loads. The Output Enables

(

OE1) and (OE2) control the Three-State Outputs. If either

OE1 or OE2 is HIGH the outputs will be in the high imped-

ance state. For data output

OE1 and OE2 both must be LOW.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC540F3A -55 to 125 20 Ld CERDIP

CD54HC541F3A -55 to 125 20 Ld CERDIP

CD54HCT541F3A -55 to 125 20 Ld CERDIP

CD74HC540E -55 to 125 20 Ld PDIP

CD74HC540M -55 to 125 20 Ld SOIC

CD74HC540M96 -55 to 125 20 Ld SOIC

CD74HC541E -55 to 125 20 Ld PDIP

CD74HC541M -55 to 125 20 Ld SOIC

CD74HC541M96 -55 to 125 20 Ld SOIC

CD74HC541PW -55 to 125 20 Ld TSSOP

CD74HC541PWR -55 to 125 20 Ld TSSOP

CD74HCT540E -55 to 125 20 Ld PDIP

CD74HCT540M -55 to 125 20 Ld SOIC

CD74HCT540M96 -55 to 125 20 Ld SOIC

CD74HCT541E -55 to 125 20 Ld PDIP

CD74HCT541M -55 to 125 20 Ld SOIC

CD74HCT541M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

January 1998 - Revised July 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC540, CD74HCT540,

CD54/74HC541, CD54/74HCT541

High-Speed CMOS Logic

Octal Buffer and Line Drivers, Three-State

[ /Title

(CD74

HC540

D74

HCT54

CD74

HC541

D74

HCT54

Summary of content (20 pages)

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[ /Title (CD74 HC540 , CD74 HCT54 0, CD74 HC541 , CD74 HCT54 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January 1998 - Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State Features Description • ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting The ’HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads.
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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Pinouts CD54HC540 (CERDIP) CD74HC540, CD74HCT540 (PDIP, SOIC) TOP VIEW OE 1 A0 2 19 OE2 A1 3 18 Y0 A2 4 17 Y1 A3 5 16 Y2 A4 6 15 Y3 A5 7 14 Y4 A6 8 13 Y5 A7 9 12 Y6 GND 10 11 Y7 CD54HC541, CD54HCT541 (CERDIP) CD74HC541 (PDIP, SOIC, TSSOP) CD74HCT541 (PDIP, SOIC) TOP VIEW 20 VCC OE1 1 A0 2 19 OE2 A1 3 18 Y0 A2 4 17 Y1 A3 5 16 Y2 A4 6 15 Y3 A5 7 14 Y4 A6 8 13 Y5 A7 9 12 Y6 GND 10 11 Y7 Functional D
PAGE 3
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 TRUTH TABLE INPUTS OUTPUTS OE1 OE2 An 540 541 L L H L H H X X Z Z X H X Z Z L L L H L H = HIGH Voltage Level L = LOW Voltage Level X= Don’t Care Z = High Impedance 3
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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . .
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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 µA Three- State Leakage Current IOZ VIL or VIH VO = VCC or GND 6 - - ±0.5 - ±5.0 - ±10 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.
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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 110 - 140 - 165 ns 4.5 - - 22 - 28 - 33 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 19 - 24 - 28 ns CL = 50pF 2 - - 115 - 145 - 175 ns 4.
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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Output Capacitance CO - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 3, 4) (540, 541) CPD CL = 15pF 5 - 55 - - - - - pF PARAMETER NOTES: 3. CPD is used to determine the dynamic power consumption, per channel. 4.
PAGE 8
Test Circuits and Waveforms OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE (Continued) IC WITH THREESTATE OUTPUT OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC540M96 Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC541M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC540M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC541M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC541PWR TSSOP PW 20 2000 367.0 367.0 38.0 CD74HCT540M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT541M96 SOIC DW 20 2000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.