Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

 

   

  

SCLS455C − FEBRUARY 2001 − REVISED MAY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 4.5-V to 5.5-V V

Operation

D Wide Operating Temperature Range of

−55°C to 125°C

D Balanced Propagation Delays and

Transition Times

D Standard Outputs Drive Up To 10 LS-TTL

Loads

D Significant Power Reduction Compared to

LS-TTL Logic ICs

D Inputs Are TTL-Voltage Compatible

description/ordering information

The ’HCT573 devices are octal transparent

D-type latches. When the latch-enable (LE) input

is high, the Q outputs follow the data (D) inputs.

When LE is low, the Q outputs are latched at the

logic levels of the D inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high

or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive bus lines without

interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − E Tube CD74HCT573E CD74HCT573E

SSOP − DB Tape and reel CD74HCT573DBR HK573

−55°C to 125°C

SOIC − M

Tube CD74HCT573M

HCT573M

−55 C to 125 C

SOIC − M

Tape and reel CD74HCT573M96

HCT573M

CDIP − F Tube CD54HCT573F3A CD54HCT573F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CD54HCT573 ...F PACKAGE

CD74HCT573 . . . DB, E, OR M PACKAGE

(TOP VIEW)

GND

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Summary of content (15 pages)

PAGE 1
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 D 4.5-V to 5.5-V VCC Operation D Wide Operating Temperature Range of −55°C to 125°C CD54HCT573 . . . F PACKAGE CD74HCT573 . . .
PAGE 2
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage VO ∆t/∆v Output voltage TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 High-level input voltage 2 2 Input voltage Input transition rise or fall rate 2 UNIT V V 0.8 0.8 0.
PAGE 4
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range, VCC = 4.
PAGE 5
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT 3V 1.3 V Input 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.3 V 1.3 V 0V 0V tsu trec Data 1.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HCT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 CD74HCT573M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HCT573DBR CD74HCT573M96 SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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