Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Push pull SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS191C

Features

• Buffered Inputs

• Asynchronous Parallel Load

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC597 and CD74HCT597 are high-speed silicon gate

CMOS devices that are pin-compatible with the LSTTL 597

devices. Each device consists of an 8-flip-flop input register

and an 8-bit parallel-in/serial-in, serial-out shift register. Each

load input (

PL) shifts parallel stored data asynchronously into

the shift register. A “low” master input (

MR) clears the shift

through the shift register when

PL is high.

Pinout

CD54HC597

(CERDIP)

CD74HC597

(PDIP, SOIC, SOP)

CD74HCT597

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE (

C) PACKAGE

CD54HC597F3A -55 to 125 16 Ld CERDIP

CD74HC597E -55 to 125 16 Ld PDIP

CD74HC597M -55 to 125 16 Ld SOIC

CD74HC597MT -55 to 125 16 Ld SOIC

CD74HC597M96 -55 to 125 16 Ld SOIC

CD74HC597NSR -55 to 125 16 Ld SOP

CD74HCT597E -55 to 125 16 Ld PDIP

CD74HCT597M -55 to 125 16 Ld SOIC

CD74HCT597MT -55 to 125 16 Ld SOIC

CD74HCT597M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

GND

January 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC597, CD74HC597,

CD74HCT597

High-Speed CMOS Logic

8-Bit Shift Register with Input Storage

[

/Title

(

CD74

C597

D74

CT59

)

Sub-

ect

(

High

peed

MOS

Summary of content (20 pages)

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[ /Title (CD74 HC597 , CD74 HCT59 7) /Subject (High Speed CMOS CD54HC597, CD74HC597, CD74HCT597 Data sheet acquired from Harris Semiconductor SCHS191C High-Speed CMOS Logic 8-Bit Shift Register with Input Storage January 1998 - Revised October 2003 Features Description • Buffered Inputs The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices.
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CD54HC597, CD74HC597, CD74HCT597 Functional Diagram DS D0 14 15 1 D1 2 D2 PARALLEL DATA INPUTS 3 D3 8 F/F STORAGE REG. 5 4 D4 D5 6 D6 7 D7 STCP 8-BIT SHIFT REG.
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CD54HC597, CD74HC597, CD74HCT597 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54HC597, CD74HC597, CD74HCT597 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.
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CD54HC597, CD74HC597, CD74HCT597 Prerequisite for Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 60 - - 75 - - 90 - - ns 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns 2 80 - - 100 - - 120 - - ns 4.
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CD54HC597, CD74HC597, CD74HCT597 Prerequisite for Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DS to SHCP Setup Time Dn to STCP Setup Time tH 4.5 10 - - 13 - - 15 - - ns STCP to SHCP Hold Time tH 4.5 0 - - 0 - - 0 - - ns DS to SHCP Hold Time Dn to STCP Hold Time tH 4.5 3 - - 3 - - 3 - - ns MR to SHCP Removal Time tREM 4.
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CD54HC597, CD74HC597, CD74HCT597 Switching Specifications Input tr, tf = 6ns PARAMETER MR to Q7 Output Transition Time Input Capacitance Power Dissipation Capacitance, (Notes 3, 4) (Continued) 25oC -40oC to 85oC -55oC to 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 4.5 - - 44 - 55 - 66 ns CL = 15pF 5 - 18 - - - - - ns tTLH, tTHL CL = 50pF 4.
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CD54HC597, CD74HC597, CD74HCT597 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.
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CD54HC597, CD74HC597, CD74HCT597 Timing Diagram SHIFT CLOCK SHCP SERIAL DATE DS MASTER RESET MR PARALLEL LOAD PL STORAGE CLOCK STCP PARALLEL DATA INPUTS D0 H L L D1 L L L D2 H L L D3 L L L D4 H L H D5 H L H D6 L L L D7 H H H Q7 L L H L H H L H L H L H L L L H L H H RESET SHIFT REGISTER SERIAL SHIFT SERIAL SHIFT LOAD FLIP-FLOPS PARALLEL LOAD SHIFT REGISTER LOAD FLIP-FLOPS 9 SERIAL SHIFT PARALLEL LOAD SHIFT REGISTER SERIAL SHIFT PARALLEL LOAD FLIP-
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC597M96 Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC597NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HCT597M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC597M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC597NSR SO NS 16 2000 367.0 367.0 38.0 CD74HCT597M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.