Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential DIP 14

Data sheet acquired from Harris Semiconductor

SCHS124D

Features

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

• Typical f

MAX

= 50MHz at V

= 5V, C

= 15pF,

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC74 and ’HCT74 utilize silicon gate CMOS technology

to achieve operating speeds equivalent to LSTTL parts.

They exhibit the low power consumption of standard CMOS

integrated circuits, together with the ability to drive 10 LSTTL

loads.

This ﬂip-ﬂop has independent DATA,

SET, RESET and

CLOCK inputs and Q and

Q outputs. The logic level present

at the data input is transferred to the output during the

positive-going transition of the clock pulse.

SET and RESET

are independent of the clock and are accomplished by a low

level at the appropriate input.

The HCT logic family is functionally as well as pin compatible

with the standard LS logic family.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC74F3A -55 to 125 14 Ld CERDIP

CD54HCT74F3A -55 to 125 14 Ld CERDIP

CD74HC74E -55 to 125 14 Ld PDIP

CD74HC74M -55 to 125 14 Ld SOIC

CD74HC74MT -55 to 125 14 Ld SOIC

CD74HC74M96 -55 to 125 14 Ld SOIC

CD74HCT74E -55 to 125 14 Ld PDIP

CD74HCT74M -55 to 125 14 Ld SOIC

CD74HCT74MT -55 to 125 14 Ld SOIC

CD74HCT74M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC74, CD74HC74,

CD54HCT74, CD74HCT74

Dual D Flip-Flop with Set and Reset

Positive-Edge Trigger

[ /Title

(CD54H

C74,

CD74H

C74,

CD74H

CT74)

/Subject

(Dual D

Flip-

Flop

with Set

January 1998 - Revised September 2003

Summary of content (17 pages)

PAGE 1
[ /Title (CD54H C74, CD74H C74, CD74H CT74) /Subject (Dual D FlipFlop with Set CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Data sheet acquired from Harris Semiconductor SCHS124D Dual D Flip-Flop with Set and Reset Positive-Edge Trigger January 1998 - Revised September 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The ’HC74 and ’HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts.
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Pinout CD54HC74, CD54HCT74 (CERDIP) CD74HC74, CD74HCT74 (PDIP, SOIC) TOP VIEW 1R 1 14 VCC 1D 2 13 2R 1CP 3 12 2D 1S 4 11 2CP 1Q 5 10 2S 1Q 6 9 2Q GND 7 8 2Q Functional Diagram 1 RESET R 2 DATA 5 Q D F/F 1 3 CLOCK 6 Q CP S 4 SET RESET 13 R 12 11 Q F/F 2 CP CLOCK S SET 9 D DATA 10 8 Q GND = PIN 7 VCC = PIN 14 TRUTH TABLE INPUTS OUTPUTS SET RESET CP D Q Q L H X X H L H L X X L H L L X X H (Note 1) H (Note 1) H
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 4 - 40 - 80 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Prerequisite For Switching Specifications PARAMETER Hold Time (Figure 5) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tH - 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns 2 30 - - 40 - 45 - ns 4.
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CP Frequency fMAX CL = 15pF 5 - 50 - - - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 25 - - - - - pF PARAMETER HCT TYPES Propagation Delay, CP to Q, Q (Figure 4) tPLH, tPHL CL = 50pF 4.
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CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC74M96 SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC74MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT74M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC74M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC74MT SOIC D 14 250 367.0 367.0 38.0 CD74HCT74M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HCT74MT SOIC D 14 250 367.0 367.0 38.
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