Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Comparator SOIC 16 No. of bits 4 AB 4.5 V

Data sheet acquired from Harris Semiconductor

SCHS136E

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 13ns (Data to Output at

= 5V, C

= 15pF, T

= 25

• Serial or Parallel Expansion Without External Gating

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30%of V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC85, CD54HCT85 (CERDIP)

CD74HC85 (PDIP, SOIC, SOP, TSSOP)

CD74HCT85 (PDIP, SOIC)

TOP VIEW

Description

The ’HC85 and ’HCT85 are high speed magnitude

comparators that use silicon-gate CMOS technology to

achieve operating speeds similar to LSTTL with the low

power consumption of standard CMOS integrated circuits.

These 4-bit devices compare two binary, BCD, or other

monotonic codes and present the three possible magnitude

results at the outputs (A > B, A < B, and A = B). The 4-bit

input words are weighted (A0 to A3 and B0 to B3), where A3

and B

are the most signiﬁcant bits.

The devices are expandable without external gating, in both

serial and parallel fashion. The upper part of the truth table

indicates operation using a single device or devices in a

serially expanded application. The parallel expansion

scheme is described by the last three entries in the truth

table.

(A < B) IN

(A = B) IN

(A > B) IN

(A > B) OUT

(A = B) OUT

GND

(A < B) OUT

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC85F3A -55 to 125 16 Ld CERDIP

CD54HCT85F3A -55 to 125 16 Ld CERDIP

CD74HC85E -55 to 125 16 Ld PDIP

CD74HC85M -55 to 125 16 Ld SOIC

CD74HC85MT -55 to 125 16 Ld SOIC

CD74HC85M96 -55 to 125 16 Ld SOIC

CD74HC85NSR -55 to 125 16 Ld SOP

CD74HC85PW -55 to 125 16 Ld TSSOP

CD74HC85PWR -55 to 125 16 Ld TSSOP

CD74HC85PWT -55 to 125 16 Ld TSSOP

CD74HCT85E -55 to 125 16 Ld PDIP

CD74HCT85M -55 to 125 16 Ld SOIC

CD74HCT85MT -55 to 125 16 Ld SOIC

CD74HCT85M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

August 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC85, CD74HC85,

CD54HCT85, CD74HCT85

High-Speed CMOS Logic

4-Bit Magnitude Comparator

[

/Title

(

CD74

C85,

D74

CT85

)

Sub-

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(

High

peed

MOS

ogic

-Bit

agni-

ude

om-

ara-

Summary of content (21 pages)

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[ /Title (CD74 HC85, CD74 HCT85 ) /Subject (High Speed CMOS Logic 4-Bit Magnitude Compara- CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Data sheet acquired from Harris Semiconductor SCHS136E High-Speed CMOS Logic 4-Bit Magnitude Comparator August 1997 - Revised October 2003 Features Description • Buffered Inputs and Outputs The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 PFunctional Diagram 15 A3 13 A2 12 A1 10 A0 (A < B) IN (A = B) IN (A > B) IN B3 7 2 3 6 4 5 (A < B) OUT (A = B) OUT (A > B) OUT 1 14 B2 11 B1 9 B0 TRUTH TABLE COMPARING INPUTS A3, B3 A2, B2 A1, B1 CASCADING INPUTS OUTPUTS A0, B0 A>B AB A B3 X X X X X X H L L A3 < B3 X X X X X X L H L A3 = B3 A2 >B2 X X X X X H L L A3 = B3 A2 < B2 X X X X X L H L A
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . .
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Switching Specifications Input tr, tf = 6ns PARAMETER (Continued) TEST CONDITIONS SYMBOL (A > B) IN, (A < B) IN, (A = B) IN tPLH, tPHL CL = 50pF to (A > B) OUT, (A < B) OUT (A > B) IN to (A = B) OUT Output Transition Times (Figure 1) CPD CIN VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 140 - 175 - 210 ns 4.
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Test Circuits and Waveforms GND VCC GND LEAST SIGNIFICANT 4-BITS OF EACH WORD A0 A1 A2 A3 B0 B1 B2 B3 (A > B) IN (A = B) IN (A < B) IN A0 A1 CD74HC85 A2 CD74HCT85 A3 B0 B1 B2 B3 (A > B) IN (A = B) IN (A < B) IN A4 A5 A6 A7 B4 B5 B6 B7 MOST SIGNIFICANT 4-BITS OF EACH WORD A4 A5 A6 A7 B4 B5 B6 B7 A0 A1 A2 A3 B0 B1 B2 B3 CD74HC85 CD74HCT85 (A > B) OUT (A = B) OUT (A < B) OUT (A > B) IN (A = B) IN (A < B) IN A0 A1 A2 A3 B0 B1 B2 B3 FIGURE 3.
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CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Test Circuits and Waveforms B1 A1 B0 A0 GND VCC GND CD74HC85 B3 CD74HCT85 A3 B2 A2 (A < B) OUT B1 (A = B) OUT A1 (A > B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN B6 A6 B5 A5 B4 A4 B3 A3 B2 GND A2 CD74HC85 B3 CD74HCT85 A3 B2 A2 (A < B) OUT B1 (A = B) OUT A1 (A > B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN B11 A11 B10 A10 B9 A9 B8 A8 B7 GND A7 CD74HC85 B3 CD74HCT85 A3 B2 A2 (A < B) OUT B1 (A = B) OUT A1 (A > B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN NC
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC85M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC85NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC85PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC85M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC85NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC85PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC85PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT85M96 SOIC D 16 2500 333.2 345.9 28.
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