User manual

Watchdog Timer Introduction
10-3Watchdog Timer, Watchdog Timer+
Figure 10−1. Watchdog Timer Block Diagram
WDTQn
Y
1
2
3
4
Q6
Q9
Q13
Q15
16−bit
Counter
CLK
A
B
1
1
AEN
PUC
SMCLK
ACLK
Clear
Password
Compare
0
0
0
0
1
1
1
1
WDTCNTCL
WDTTMSEL
WDTNMI
WDTNMIES
WDTIS1
WDTSSEL
WDTIS0
WDTHOLD
EQU
EQU
Write Enable
Low Byte
R / W
MDB
LSB
MSB
WDTCTL
(Asyn)
Int.
Flag
Pulse
Generator
SMCLK Active
MCLK Active
ACLK Active
16−bit
†MSP430x42x and MSP430FE42x devices only
Fail-Safe
Logic
†
Clock
Request
Logic
†
MCLK
†