TMS320DM646x DMSoC ARM Subsystem Reference Guide Literature Number: SPRUEP9A May 2008
SPRUEP9A – May 2008 Submit Documentation Feedback
Contents Preface.............................................................................................................................. 11 1 1.1 1.2 ............................................................................................................. 13 Overview..................................................................................................................... 14 ARM Subsystem in TMS320DM646x DMSoC .........................................................................
www.ti.com 5.4.3 PLL Control Register (PLLCTL) ................................................................................. 47 5.4.4 PLL Multiplier Control Register (PLLM) 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.4.11 5.4.12 5.4.13 5.4.14 5.4.15 5.4.16 48 49 50 51 52 52 53 54 55 57 58 59 60 .............................................................................. 61 6 Power and Sleep Controller (PSC) 6.1 Introduction ........................................................................
www.ti.com 7.4.2 DSP Sleep Modes ................................................................................................. 82 7.5 I/O Management ............................................................................................................ 83 7.6 USB Phy Power Down ..................................................................................................... 83 7.5.1 3.3 V I/O Power-Down ....................................................................................
www.ti.com 9.7 9.6.4 Transport Stream Interface (TSIF) Control ................................................................... 106 9.6.5 Video Source Clock Control and Disable ..................................................................... 106 9.6.6 PWM Control ..................................................................................................... 106 9.6.7 EDMA3 Transfer Controller (EDMA3TC) Burst Size Configuration ....................................... 106 9.6.
www.ti.com List of Figures 1-1 2-1 3-1 3-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 TMS320DM6467 DMSoC Block Diagram ............................................................................... TMS320DM646x DMSoC ARM Subsystem Block Diagram .......................................................... TCM Status Register ...............
www.ti.com 8-16 8-17 8-18 8-19 8-20 8-21 8-22 10-1 10-2 12-1 8 Interrupt Priority Register 1 (INTPRI1) .................................................................................. 98 Interrupt Priority Register 2 (INTPRI2) .................................................................................. 99 Interrupt Priority Register 3 (INTPRI3) .................................................................................. 99 Interrupt Priority Register 4 (INTPRI4) ............................
www.ti.com List of Tables 3-1 3-2 3-3 3-4 3-5 3-6 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 7-1 8-1 8-2 8-3 8-4 Exception Vector Table for ARM ......................................................................................... Different Address Types in ARM System ............................................................................... ITCM/DTCM Memory Map ........
www.ti.com 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 9-1 9-2 9-3 10-1 10-2 10-3 10-4 12-1 12-2 A-1 10 Interrupt Request Status Register 0 (IRQ0) Field Descriptions ...................................................... 93 Interrupt Request Status Register 1 (IRQ1) Field Descriptions ...................................................... 93 Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions..................................
Preface SPRUEP9A – May 2008 Read This First About This Manual This document describes the ARM subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
Related Documentation From Texas Instruments www.ti.com efficiency. The internal memory architecture in the C621x/C671x/C64x DSPs is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.
Chapter 1 SPRUEP9A – May 2008 Introduction Topic 1.1 1.2 .................................................................................................. Page Overview .................................................................................. 14 ARM Subsystem in TMS320DM646x DMSoC .................................
Overview 1.1 www.ti.com Overview The TMS320DM646x Digital Media System-on-Chip (DMSoC) contains two primary CPU cores: 1) an ARM RISC CPU for general purpose processing and systems control and 2) a powerful DSP to efficiently handle image, video, and audio processing tasks.
Chapter 2 SPRUEP9A – May 2008 ARM Subsystem Overview Topic 2.1 2.2 2.3 .................................................................................................. Page Purpose of the ARM Subsystem ................................................. 16 Components of the ARM Subsystem ........................................... 16 References ...............................................................................
Purpose of the ARM Subsystem 2.1 www.ti.com Purpose of the ARM Subsystem The ARM Subsystem contains the components required to provide the ARM926EJ-S (ARM) master control of the TMS320DM646x DMSoC system. In general, the ARM is responsible for configuration and control of the overall DM646x DMSoC system, including the DSP Subsystem and a majority of the peripherals and external memories.
References www.ti.com • Video Port Interface (VPIF) Figure 2-1 shows the functional block diagram of the DM646x DMSoC ARM Subsystem. The DM646x DMSoC architecture uses two primary bus subsystems to transfer data within the system: • • The DMA bus (sometimes called data bus) is used for data transfer between subsystems and modules. The CFG bus (or configuration bus) is used to read/write to peripheral registers in various modules for configuration. Figure 2-1.
ARM Subsystem Overview SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 3 SPRUEP9A – May 2008 ARM Core Topic 3.1 3.2 3.3 3.4 3.5 3.6 3.7 .................................................................................................. Introduction.............................................................................. Operating States/Modes ............................................................. Processor Status Registers ........................................................ Exceptions and Exception Vectors ...........................................
Introduction 3.1 www.ti.com Introduction This chapter describes the ARM core and its associated memories. The ARM core consists of the following components: • ARM926EJ-S - 32-bit RISC processor • 16-KB Instruction cache • 8-KB Data cache • Memory Management Unit (MMU) • CP15 to control MMU, cache, etc.
Operating States/Modes www.ti.com 3.2 Operating States/Modes The ARM can operate in two states: ARM (32-bit) mode and Thumb (16-bit) mode. You can switch the ARM926EJ-S processor between ARM mode and Thumb mode using the BX instruction. The ARM can operate in the following modes: • User mode (USR): Non-privileged mode, usually for the execution of most application programs.
Exceptions and Exception Vectors 3.4 www.ti.com Exceptions and Exception Vectors Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that occur in an ARM system are given below: • Reset exception: processor reset • FIQ interrupt: fast interrupt • IRQ interrupt: normal interrupt • Abort exception: abort indicates that the current memory access could not be completed. The abort could be a pre-fetch abort or a data abort.
www.ti.com 3.5 The 16-BIS/32-BIS Concept The 16-BIS/32-BIS Concept The key idea behind 16-BIS is that of a super-reduced instruction set.
Co-Processor 15 (CP15) 3.6 www.ti.com Co-Processor 15 (CP15) The system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Units (MMUs), and many system functions. The CP15 registers are only accessible with MRC and MCR instructions by the ARM in a privileged mode like supervisor mode or system mode. 3.6.1 Addresses in an ARM926EJ-S System Three different types of addresses exist in an ARM926EJ-S system.
Co-Processor 15 (CP15) www.ti.com 3.6.3 Caches and Write Buffer The ARM926EJ-S processor includes: • An Instruction cache (Icache) • A Data cache (Dcache) • A write buffer The size of the data cache is 8 KB, instruction cache is 16 KB, and write buffer is 17 bytes.
Tightly-Coupled Memory 3.7 www.ti.com Tightly-Coupled Memory The ARM926EJ-S has a tightly-coupled memory interface enabling separate instruction and data TCM to be interfaced to the ARM. TCMs are meant for storing real-time and performance critical code. The DM646x DMSoC supports both instruction TCM (I-TCM) and data TCM (D-TCM). The instruction TCM is located at 0000:0000h to 0000:9FFFh; the data TCM is located at 0001:0000h to 0001:9FFFh, as shown in Table 3-3. Table 3-3.
Tightly-Coupled Memory www.ti.com The format of the data in the TCM region setup register is shown in Figure 3-2. Figure 3-2. TCM Region Setup Register 31 16 ADDRESS 15 12 11 6 ADDRESS 5 2 Reserved (000000) SIZE 1 0 0 ENB Table 3-5. TCM Region Setup Register Field Descriptions Bit Field Value 31-12 ADDRESS 11-6 Reserved 5-2 SIZE 1 0 0 ENB Description 0-FFFFFh Base Address.
Tightly-Coupled Memory www.ti.com Example 3-2. TMS320DM646x ITCM Register c9 Programming ; Read ITCM MRC p15, #00, R3, c9, c1, #1 NOP NOP ; Enable ITCM MOV R0, #0x1; MCR p15, #00, R0, c9, c1, #1 NOP NOP ; Read Back the ITCM value to check the ITCM Enable function MRC p15, #00, R4, c9, c1, #1 NOP NOP Example 3-3. TMS320DM646x DTCM Register c9 Programming DTCM_BASE_ADDR .
Chapter 4 SPRUEP9A – May 2008 System Memory Topic 4.1 4.2 .................................................................................................. Page Memory Map ............................................................................. 30 Memory Interfaces Overview ......................................................
Memory Map 4.1 www.ti.com Memory Map The TMS320DM646x DMSoC has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development, a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. For detailed memory-map information, see the device-specific data manual. 4.1.
Memory Interfaces Overview www.ti.com • • • • • 3 Universal Asynchronous Receiver/Transmitters (UART) (one with modem control) Universal Serial Bus (USB) Controller Video Data Conversion Engine (VDCE) VLYNQ Interface 2 Video Port Interfaces (VPIF) The ARM Subsystem also has access to the following internal peripherals: • System Module • PLL Controllers • Power Sleep Controller (PSC) • ARM Interrupt Controller (AINTC) 4.
Memory Interfaces Overview 4.2.2.1 www.ti.com Asynchronous EMIF (EMIFA) The asynchronous EMIF (EMIFA) provides both the EMIFA and NAND interfaces. Four chip selects are provided. Each is individually configurable to provide either EMIFA or NAND support.
www.ti.com 4.2.2.4 Memory Interfaces Overview Peripheral Component Interface (PCI) The PCI module allows communication with devices complaint to the PCI Local Bus Specification (revision 2.3) via a 32-bit address/data bus operating at speeds up to 33 MHZ. The PCI module supports the following features: • PCI Local Bus Specification (revision 2.
System Memory SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 5 SPRUEP9A – May 2008 PLL Controller Topic 5.1 5.2 5.3 5.4 .................................................................................................. PLL Module .............................................................................. PLL1 Control ............................................................................ PLL2 Control ............................................................................ PLL Controller Register Map ............................................
PLL Module 5.1 www.ti.com PLL Module The TMS320DM646x DMSoC has two PLL controllers that provide clocks to different parts of the system (see Figure 5-1). PLL1 provides clocks (though various dividers) to most of the components of the DMSoC. PLL2 is dedicated to the DDR2 memory controller. The recommended reference clock is a 27-MHZ crystal input. See the device-specific data manual for the supported input clocks.
PLL Module www.ti.com Figure 5-1.
PLL1 Control 5.2 www.ti.com PLL1 Control PLL1 supplies the primary DM646x DMSoC system clock. Software controls the PLL1 operation through the system PLL controller 1 (PLLC1) registers (base address: 1C4 0800h). Figure 5-2 shows the customization of PLL1 in the DM646x DMSoC. • The SYSCLK dividers are programmable (see Table 5-1).
PLL1 Control www.ti.com 5.2.1 Device Clock Generation PLLC1 generates several clocks from the PLL1 output clock for use by the various processors and modules. These are summarized in Table 5-1. Note: On the DM646x DMSoC, all PLL1 SYSCLKn dividers are programmable but you should not change the divider value to maintain the clock ratios between various modules of the device. You should only use the power-up default divider values for all PLL1 SYSCLKn dividers for normal device operation.
PLL1 Control 5.2.2.1 www.ti.com Initialization to PLL Mode from PLL Power Down If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow this procedure to change the PLL1 frequencies. The recommendation is to stop all peripheral operation before changing the PLL1 frequency, with the exception of the ARM and DDR2 memory controller. The ARM must be operational to program the PLL controller. The DDR2 memory controller operates off of the clock from PLLC2. 1.
PLL2 Control www.ti.com 5.3 PLL2 Control PLL2 provides the clock from which the DDR2 memory controller clock is derived. This is a separate clock system from the PLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of the core clock rates to save power while maintaining the required minimum clock rate for DDR2. PLL2 must be configured to output a 2x clock to the DDR2 PHY interface.
PLL2 Control www.ti.com 5.3.1 Device Clock Generation PLLC2 generates the clock from the PLL2 output clock for use by the DDR2 memory controller, as shown in Table 5-2. The SYSCLK1 output clock divider value defaults to /1, resulting in a 594-MHZ DDR Phy clock (297-MHZ DDR). It can be modified by software (using the RATIO bit in PLLDIV1) in combination with other PLL multipliers to achieve the desired DDR2 memory controller clock rate. Table 5-2.
PLL2 Control www.ti.com 5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset This section discusses the steps to change the PLL2 frequency when the DDR2 memory controller is already out of reset. 1. Stop DDR2 memory controller accesses and purge any outstanding requests. 2. Put the DDR2 memory in self-refresh mode and stop the DDR2 memory controller clock.
PLL2 Control 5.3.2.3 www.ti.com Changing PLL Multiplier If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time is previously met (step 7 in Section 5.3.2.2), follow this procedure to change PLL2 multiplier. 1. Before changing the PLL frequency, switch to PLL bypass mode: a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect. b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode). c.
PLL Controller Register Map www.ti.com 5.4 PLL Controller Register Map Table 5-3. PLL and Reset Controller Module Instance Table Instance ID Base Address End Address Size 0 1C4 0800h 1C4 0BFFh 400h 1 1C4 0C00h 1C4 0FFFh 400h Table 5-4 lists the memory-mapped registers for the PLL and Reset Controller. See the device-specific data manual for the memory address of these registers. Table 5-4.
PLL Controller Register Map www.ti.com 5.4.1 Peripheral ID Register (PID) The peripheral ID register (PID) is shown in Figure 5-4 and described in Table 5-5. Figure 5-4. Peripheral ID Register (PID) 31 24 23 16 Reserved TYPE R-0 R-1h 15 8 7 0 CLASS REV R-8h R-2h LEGEND: R = Read only; -n = value after reset Table 5-5.
PLL Controller Register Map www.ti.com 5.4.3 PLL Control Register (PLLCTL) The PLL control register (PLLCTL) is shown in Figure 5-6 and described in Table 5-7. Figure 5-6. PLL Control Register (PLLCTL) 31 16 Reserved R-0 15 5 4 3 2 1 0 Reserved 9 CLKMODE 8 Reserved 7 6 PLLENSRC PLLDIS PLLRST Rsvd PLLPWRDN PLLEN R-0 R/W-0 R-3h R/W-1 R/W-1 R/W-0 R-0 R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-7.
PLL Controller Register Map www.ti.com 5.4.4 PLL Multiplier Control Register (PLLM) The PLL multiplier control register (PLLM) is shown in Figure 5-7 and described in Table 5-8. Figure 5-7. PLL Multiplier Control Register (PLLM) 31 16 Reserved R-0 15 5 4 0 Reserved PLLM R-0 R/W-15h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-8.
PLL Controller Register Map www.ti.com 5.4.5 PLL Controller Divider 1 Register (PLLDIV1) The PLL controller divider 1 register (PLLDIV1) is shown in Figure 5-8 and described in Table 5-9. Divider 1 controls the divider for SYSCLK1. Note: On the DM646x DMSoC, all PLL1 SYSCLKn dividers are programmable but you should not change the divider value to maintain the clock ratios between various modules of the device.
PLL Controller Register Map www.ti.com 5.4.6 PLL Controller Divider 2 Register (PLLDIV2) The PLL controller divider 2 register (PLLDIV2) is shown in Figure 5-9 and described in Table 5-10. Divider 2 controls the divider for SYSCLK2. PLLDIV2 is not used on PLL2. Note: On the DM646x DMSoC, all PLL1 SYSCLKn dividers are programmable but you should not change the divider value to maintain the clock ratios between various modules of the device.
PLL Controller Register Map www.ti.com 5.4.7 PLL Controller Divider 3 Register (PLLDIV3) The PLL controller divider 3 register (PLLDIV3) is shown in Figure 5-10 and described in Table 5-11. Divider 3 controls the divider for SYSCLK3. PLLDIV3 is not used on PLL2. Note: On the DM646x DMSoC, all PLL1 SYSCLKn dividers are programmable but you should not change the divider value to maintain the clock ratios between various modules of the device.
PLL Controller Register Map www.ti.com 5.4.8 Bypass Divider Register (BPDIV) The bypass divider register (BPDIV) is shown in Figure 5-11 and described in Table 5-12. Bypass divider controls the divider for SYSCLKBP. BPDIV is not used on PLL2. Figure 5-11. Bypass Divider Register (BPDIV) 31 16 Reserved R-0 15 14 5 4 0 BPDEN Reserved RATIO R/W-1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-12.
PLL Controller Register Map www.ti.com 5.4.10 PLL Controller Status Register (PLLSTAT) The PLL controller status register (PLLSTAT) is shown in Figure 5-13 and described in Table 5-14. Figure 5-13. PLL Controller Status Register (PLLSTAT) 31 16 Reserved R-0 15 2 1 0 Reserved 3 STABLE Reserved GOSTAT R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 5-14.
PLL Controller Register Map www.ti.com 5.4.11 PLL Controller Clock Align Control Register (ALNCTL) The PLL controller clock align control register (ALNCTL) is shown in Figure 5-14 and described in Table 5-15. Indicates which SYSCLKs need to be aligned for proper device operation. Figure 5-14.
PLL Controller Register Map www.ti.com 5.4.12 PLLDIV Ratio Change Status Register (DCHANGE) The PLLDIV ratio change status register (DCHANGE) is shown in Figure 5-15 and described in Table 5-16. Indicates if SYSCLKn divide ratio has been modified. Note: On the DM646x DMSoC, all PLL1 SYSCLKn dividers are programmable but you should not change the divider value to maintain the clock ratios between various modules of the device.
PLL Controller Register Map www.ti.com Table 5-16. PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions (continued) Bit Field 3 SYS4 2 1 0 56 Value SYSCLK4 divide ratio is modified. SYSCLK4 divide ratio is changed during GO operation. For PLL1 only, not supported for PLL2. 0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is set, SYSCLK4 is not affected. 1 Ratio has been modified.
PLL Controller Register Map www.ti.com 5.4.13 Clock Enable Control Register (CKEN) The clock enable control register (CKEN) is shown in Figure 5-16 and described in Table 5-17. Clock enable control for miscellaneous output clocks. CKEN is not used on PLL2. Figure 5-16. Clock Enable Control Register (CKEN) 31 16 Reserved R-0 15 1 0 Reserved AUXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-17.
PLL Controller Register Map www.ti.com 5.4.14 Clock Status Register (CKSTAT) The clock status register (CKSTAT) is shown in Figure 5-17 and described in Table 5-18. Clock status for all clocks, except SYSCLKn. CKSTAT is not used on PLL2. Figure 5-17. Clock Status Register (CKSTAT) 31 16 Reserved R-0 15 4 3 2 1 0 Reserved BPON Reserved AUXEN R-0 R-1 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 5-18.
PLL Controller Register Map www.ti.com 5.4.15 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) is shown in Figure 5-18 and described in Table 5-19. Indicates SYSCLKn status. Actual default is determined by the actual clock status, which depends on the DnEN bit in the PLL controller divider n register (PLLDIVn). Figure 5-18.
PLL Controller Register Map www.ti.com 5.4.16 PLL Controller Divider n Registers (PLLDIV4-PLLDIV6, PLLDIV8, PLLDIV9) The PLL controller divider n register (PLLDIVn) is shown in Figure 5-19 and described in Table 5-20. PLLDIV4 controls the divider for SYSCLK4, PLLDIV5 controls the divider for SYSCLK5, PLLDIV6 controls the divider for SYSCLK6, PLLDIV8 controls the divider for SYSCLK8, and PLLDIV9 controls the divider for SYSCLK9. PLLDIVn is not used on PLL2.
Chapter 6 SPRUEP9A – May 2008 Power and Sleep Controller (PSC) Topic 6.1 6.2 6.3 6.4 6.5 6.6 .................................................................................................. Introduction.............................................................................. Power Domain and Module Topology .......................................... Executing Module State Transitions ............................................ IcePick Emulation Support in the PSC ................................
Introduction 6.1 www.ti.com Introduction In the TMS320DM646x DMSoC system, the Power and Sleep Controller (PSC) is responsible for managing transitions of clock on/off and reset. A block diagram of the PSC is shown in Figure 6-1. Many of the PSC operations are transparent to software, such as hard reset operations. However, the PSC provides you with an interface to control several important clock and reset operations. The clock and reset operations are described in this chapter.
Power Domain and Module Topology www.ti.com 6.2 Power Domain and Module Topology The DM646x DMSoC system includes only one power domain (Always On) and multiple separate modules, as shown in Figure 6-2 and summarized in Table 6-1. The Always On power domain is always in the ON state when the chip is powered-on. The Always On domain is powered by the CVDD pins of the DM646x DMSoC (see the device-specific data manual). All of the DM646x DMSoC modules reside within the Always On power domain.
Power Domain and Module Topology www.ti.com Table 6-1. Module Configuration Default State Module Number 64 Module Name Module State [STATE bit in MDSTATn in PSC] Local Reset State 0 Reserved Reserved - 1 DSP C64x+ If DSPBOOT = 0, SwRstDisable If DSPBOOT = 1, Enable DSPBOOT 2 HDVICP0 SwRstDisable - 3 HDVICP1 SwRstDisable - 4 EDMA3CC SwRstDisable - 5 EDMA3TC0 SwRstDisable - 6 EDMA3TC1 SwRstDisable - 7 EDMA3TC2 SwRstDisable - 8 EDMA3TC3 SwRstDisable - 9 USB2.
Power Domain and Module Topology www.ti.com 6.2.1 Power Domain States A power domain can only be in one of two states: ON or OFF, defined as: • ON: power to the power domain is on. • OFF: power to the power domain is off. In the DM646x DMSoC, there is only one power domain (Always On) .The Always On power domain is always in the ON state when the chip is powered-on. 6.2.
Executing Module State Transitions 6.3 www.ti.com Executing Module State Transitions The procedure for module state transitions is as follows (n corresponds to the module number, see Table 6-1 for the module numbers): • Wait for the GOSTAT[0] bit in the power domain transition status register (PTSTAT) to clear to 0. You must wait for any previously initiated transitions to finish before initiating a new transition.
PSC Interrupts www.ti.com Note: In the DM646x DMSoC, there is only one power domain (Always On), so all IcePick commands do not have any control on the power domain and only control module states and resets. When emulation tools remove the above commands, the PSC immediately executes a state transition based on the current values in the NEXT bit in the power domain control n register (PDCTLn) and the NEXT bit in the module control n register (MDCTLn), as set by software. 6.
PSC Interrupts www.ti.com 6.5.2 Interrupt Register Bits The PSC interrupt enable bits are the EMUIHBIE bit and the EMURSTIE bit in the module control n register (MDCTLn). Note: To interrupt the ARM, the ARM’s power and sleep controller interrupt (PSCINT) must also be enabled in the ARM interrupt controller (AINTC). See Chapter 8 for more information on the ARM interrupt controller.
PSC Registers www.ti.com 6.6 PSC Registers Table 6-6 lists the memory-mapped registers for the PSC. See the device-specific data manual for the memory address of these registers. Table 6-6. Power and Sleep Controller (PSC) Registers Offset Register Description 0h PID Peripheral Revision and Class Information Register Section 6.6.1 18h INTEVAL Interrupt Evaluation Register Section 6.6.2 40h MERRPR0 Module Error Pending Register 0 (modules 0-31) Section 6.6.
PSC Registers www.ti.com 6.6.1 Peripheral Revision and Class Information Register (PID) The peripheral revision and class information (PID) register is shown in Figure 6-3 and described in Table 6-7. Figure 6-3. Peripheral Revision and Class Information Register (PID) 31 30 29 28 27 16 SCHEME Reserved FUNC R-1 R-0 R-482h 15 11 10 8 7 6 5 0 RTL MAJOR CUSTOM MINOR R-3h R-1 R-0 R-5h LEGEND: R = Read only; -n = value after reset Table 6-7.
PSC Registers www.ti.com 6.6.3 Module Error Pending Register 0 (MERRPR0) The module error pending register 0 (MERRPR0) records pending error conditions for modules 0-31. MERRPR0 is shown in Figure 6-5 and described in Table 6-9. Figure 6-5. Module Error Pending Register 0 (MERRPR0) 31 0 M R- 0 LEGEND: R = Read only; -n = value after reset Table 6-9. Module Error Pending Register 0 (MERRPR0) Field Descriptions Bit Field 31-0 M[n] Value Description Module interrupt status bit for modules 0-31.
PSC Registers www.ti.com 6.6.5 Module Error Clear Register 0 (MERRCR0) The module error clear register 0 (MERRCR0) clears the corresponding interrupt bit set (M[n]) in the module error pending register 0 (MERRPR0) and the module status n register (MDSTATn) interrupt bit field for modules 0-31. MERRCR0 is shown in Figure 6-7 and described in Table 6-11. Figure 6-7. Module Error Clear Register 0 (MERRCR0) 31 0 M W-0 LEGEND: W = Write only; -n = value after reset Table 6-11.
PSC Registers www.ti.com 6.6.7 Power Domain Transition Command Register (PTCMD) The power domain transition command register (PTCMD) is shown in Figure 6-9 and described in Table 6-13. Figure 6-9. Power Domain Transition Command Register (PTCMD) 31 16 Reserved R-0 15 1 0 Reserved GO R-0 W-0 LEGEND: R = Read only; W = Write only; -n = value after reset Table 6-13.
PSC Registers www.ti.com 6.6.9 Power Domain Status Register (PDSTAT0) The power domain status register (PDSTAT0) is shown in Figure 6-11 and described in Table 6-15. Figure 6-11. Power Domain Status Register (PDSTAT0) 31 16 Reserved R-0 15 11 10 9 8 Reserved 12 EMUIHB Reserved PORDONE POR 7 Reserved 5 4 STATE 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 6-15.
PSC Registers www.ti.com 6.6.10 Power Domain Control Register (PDCTL0) The power domain control register (PDCTL0) is shown in Figure 6-12 and described in Table 6-16. Figure 6-12. Power Domain Control Register (PDCTL0) 31 16 Reserved R-0 15 10 9 Reserved 8 7 Reserved R-0 R/W-0 R/W-0 1 0 Reserved NEXT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-16.
PSC Registers www.ti.com 6.6.11 Module Status n Register (MDSTAT0-MDSTAT45) The module status n register (MDSTATn) shows the status of each module. Each module has one dedicated register. MDSTATn is shown in Figure 6-13 and described in Table 6-17. Figure 6-13.
PSC Registers www.ti.com 6.6.12 Module Control n Register (MDCTL0-MDCTL45) The module control n register (MDCTLn) provides specific control for an individual module. Each module has one dedicated register. MDCTLn is shown in Figure 6-14 and described in Table 6-18. Figure 6-14.
Power and Sleep Controller (PSC) SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 7 SPRUEP9A – May 2008 Power Management Topic 7.1 7.2 7.3 7.4 7.5 7.6 .................................................................................................. Overview .................................................................................. PSC and PLLC Overview ............................................................ Clock Management .................................................................... ARM and DSP Sleep Mode Management .....................................
Overview 7.1 www.ti.com Overview In many applications, there may be specific requirements to minimize power consumption for both power supply (or battery) and thermal considerations. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales roughly with clock frequency and the amount of computations being performed.
Clock Management www.ti.com 7.3 Clock Management 7.3.1 Module Clock ON/OFF The module clock on/off feature allows software to disable clocks to module individually, in order to reduce the module's active power consumption to 0. The DM646x DMSoC is designed in full static CMOS; thus, when a module clock stops, the module's state is preserved. When the clock is restarted, the module resumes operating from the stopping point.
ARM and DSP Sleep Mode Management www.ti.com The following sequence describes the procedure to wake up from the wait-for-interrupt mode: • To wake up from the wait-for-interrupt mode, trigger any enabled interrupt (for example, an external interrupt). • The ARM’s PC jumps to the IRQ vector and you must handle the interrupt in an interrupt service routine (ISR).
I/O Management www.ti.com 7.5 I/O Management 7.5.1 3.3 V I/O Power-Down The 3.3 V I/O drivers are fabricated out of 1.8 V transistors with design techniques that require a DC bias current. These I/O cells have a power-down mode that turns off the DC current. The VDD3P3V_PWDN register in the System Module controls power to the 3.3V I/O cells. The 3.3V I/Os are separated into functional groups for independent control different modules.
Power Management SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 8 SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) Topic 8.1 8.2 8.3 8.4 .................................................................................................. Introduction.............................................................................. Interrupt Mapping...................................................................... AINTC Methodology .................................................................. AINTC Registers ............................................
Introduction 8.1 www.ti.com Introduction The TMS320DM646x DMSoC ARM interrupt controller (AINTC) has the following features: • Supports up to 64 interrupt channels (16 external channels) • Interrupt mask for each channel • Each interrupt channel is mappable to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt.
Interrupt Mapping www.ti.com Table 8-1.
AINTC Methodology 8.3 www.ti.com AINTC Methodology AINTC methodology is illustrated in Figure 8-1 and described below. • When an interrupt occurs, the status is reflected in either the FIQn or the IRQn registers, depending upon the interrupt type selected. • Interrupts are enabled or disabled (masked) by setting the EINTn register. Note: • • Even if an interrupt is masked, the status interrupt is still reflected in the FIQn and the IRQn registers.
AINTC Methodology www.ti.com 8.3.2 Interrupt Prioritization Event priority is determined using both a fixed and a programmable prioritization scheme. The AINTC has 8 different programmable interrupt priorities. Priority 0 and priority 1 are mapped to the FIQ interrupt with priority 0 being the highest priority. Priorities 2-7 are mapped to the IRQ interrupt (priority 2 is the highest, priority 7 is the lowest). Each interrupt is mapped to a priority level using the INTPRIn registers.
AINTC Methodology www.ti.com 2. For the IRQENTRY: • If IERAW is 0, IRQENTRY reflects the state of the highest priority pending enabled IRQ interrupt. If the active IRQ interrupt is cleared in IRQn, then IRQENTRY is immediately updated with the vector of the next highest priority pending enabled IRQ interrupt. • If IERAW is 1, IRQENTRY reflects the state of the highest priority pending IRQ interrupt (enabled or not).
AINTC Registers www.ti.com Figure 8-4. Delayed Interrupt Disable CLK Event pulse INTn EINTn Disabled IRQn/FIQn Cleared IRQz/FIQz ENTRY EABASE 8.4 VECTORn EABASE AINTC Registers Table 8-2 lists the memory-mapped registers for the AINTC. See the device-specific data manual for the memory address of these registers. Table 8-2. ARM Interrupt Controller (AINTC) Registers Offset Acronym Register Description 00h FIQ0 Fast Interrupt Request Status Register 0 Section 8.4.
AINTC Registers www.ti.com 8.4.1 Fast Interrupt Request Status Register 0 (FIQ0) The fast interrupt request status register 0 (FIQ0) is shown in Figure 8-5 and described in Table 8-3. Interrupt status of INT[31:0] (if mapped to FIQ). Figure 8-5. Fast Interrupt Request Status Register 0 (FIQ0) 31 16 FIQ R/W-1 15 0 FIQ R/W-1 LEGEND: R/W = Read/Write; -n = value after reset Table 8-3.
AINTC Registers www.ti.com 8.4.3 Interrupt Request Status Register 0 (IRQ0) The interrupt request status register 0 (IRQ0) is shown in Figure 8-7 and described in Table 8-5. Interrupt status of INT[31:0] (if mapped to IRQ). Figure 8-7. Interrupt Request Status Register 0 (IRQ0) 31 16 IRQ R/W-1 15 1 0 IRQ IRQ0 R/W-1 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-5.
AINTC Registers www.ti.com 8.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY) The fast interrupt request entry address register (FIQENTRY) is shown in Figure 8-9 and described in Table 8-7. Entry address [28:0] for valid FIQ interrupt. Figure 8-9. Fast Interrupt Request Entry Address Register (FIQENTRY) 31 29 28 16 Reserved FIQENTRY R-0 R-0 15 0 FIQENTRY R-0 LEGEND: R = Read only; -n = value after reset Table 8-7.
AINTC Registers www.ti.com 8.4.7 Interrupt Enable Register 0 (EINT0) The interrupt enable register 0 (EINT0) is shown in Figure 8-11 and described in Table 8-9. Figure 8-11. Interrupt Enable Register 0 (EINT0) 31 16 EINT R/W-0 15 1 0 EINT EINT0 R/W-0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-9. Interrupt Enable Register 0 (EINT0) Field Descriptions Bit 31-1 0 Field Value Description EINT[n] EINT0 Interrupt enable for INTn.
AINTC Registers www.ti.com 8.4.9 Interrupt Operation Control Register (INTCTL) The interrupt operation control register (INTCTL) is shown in Figure 8-13 and described in Table 8-11. Figure 8-13. Interrupt Operation Control Register (INTCTL) 31 16 Reserved R-0 15 2 1 0 Reserved 3 IDMODE IERAW FERAW R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-11.
AINTC Registers www.ti.com 8.4.10 Interrupt Entry Table Base Address Register (EABASE) The interrupt entry table base address register (EABASE) is shown in Figure 8-14 and described in Table 8-12. Figure 8-14. Interrupt Entry Table Base Address Register (EABASE) 31 29 28 16 Reserved EABASE R-0 R/W-0 15 3 2 1 0 EABASE Reserved SIZE R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-12.
AINTC Registers www.ti.com 8.4.11 Interrupt Priority Register 0 (INTPRI0) The interrupt priority register 0 (INTPRI0) is shown in Figure 8-15 and described in Table 8-13. Figure 8-15.
AINTC Registers www.ti.com 8.4.13 Interrupt Priority Register 2 (INTPRI2) The interrupt priority register 2 (INTPRI2) is shown in Figure 8-17 and described in Table 8-15. Figure 8-17.
AINTC Registers www.ti.com 8.4.15 Interrupt Priority Register 4 (INTPRI4) The interrupt priority register 4 (INTPRI4) is shown in Figure 8-19 and described in Table 8-17. Figure 8-19.
AINTC Registers www.ti.com 8.4.17 Interrupt Priority Register 6 (INTPRI6) The interrupt priority register 6 (INTPRI6) is shown in Figure 8-21 and described in Table 8-19. Figure 8-21.
ARM Interrupt Controller (AINTC) SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 9 SPRUEP9A – May 2008 System Control Module Topic .................................................................................................. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 Overview of the System Control Module .................................... Device Identification ................................................................ Device Configuration ............................................................... ARM-DSP Integration ..........................................
Overview of the System Control Module 9.1 www.ti.com Overview of the System Control Module The TMS320DM646x DMSoC system control module is a system-level module containing status and top-level control logic required by the device.
www.ti.com 9.3 Device Configuration Device Configuration The system control module contains registers for controlling pin multiplexing and registers that reflect the boot configuration and boot process status. 9.3.1 Pin Multiplexing Control The DM646x DMSoC makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package.
Power Management 9.5 www.ti.com Power Management 9.5.1 VDD 3.3 V I/O Power-Down Control The VDD 3.3V I/O power-down control register (VDD3P3V_PWDN) in the System Module controls power to the 3.3 V I/O cells. The 3.3 V I/Os are separated into two groups for independent control. See the device-specific data manual for details on VDD3P3V_PWDN. 9.6 Special Peripheral Status and Control Several of the DM646x DMSoC peripherals require additional system-level control logic.
Bandwidth Management www.ti.com 9.6.8 ARM Memory Wait State Control The ARM memory wait state control register (ARMWAIT) is used to control ARM926 accesses to its TCM RAM. At normal ARM operating frequency, a wait state must be inserted when accessing TCM RAM. When the device is operating at lower speeds, performance may be increased by removing the wait state. Note that the TCM ROM will always operate with a wait state enabled. See the device-specific data manual for details on ARMWAIT. 9.
Emulation Control www.ti.com Prioritization within each switched central resource (SCR) is selected to be either fixed or dynamic. Dynamic prioritization is based on an incoming priority signal from each master. On the DM646x DMSoC, all master peripherals are programmed in the bus master priority control registers (MSTRPRIn) in the System Module. The default priority level for each bus master is listed in Table 9-2.
Clock and Oscillator Control www.ti.com 9.9 Clock and Oscillator Control The auxiliary (24 MHz) oscillator and the clock source of the CLKOUT, AUDIO_CLK0, and AUDIO_CLK1 outputs are controlled by the clock and oscillator control register (CLKCTL). See the device-specific data manual for details on CLKCTL. 9.10 System Control Register Descriptions Table 9-3 lists the memory-mapped registers for the system control.
System Control Module SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 10 SPRUEP9A – May 2008 Reset Topic .................................................................................................. 10.1 10.2 10.3 10.4 Reset Overview ....................................................................... Reset Pins .............................................................................. Types of Reset ........................................................................ Default Device Configurations ..................................................
Reset Overview www.ti.com 10.1 Reset Overview There are six types of reset in the TMS320DM646x DMSoC. The types of reset differ by how they are initiated and/or by their effect on the device. Each type is briefly described in Table 10-1 and further described in the following sections. Table 10-1. Reset Types Type Initiator Effect Power-on reset (POR) POR pin active low Total reset of the chip (cold reset). Resets all modules including memory and emulation. Total reset of chip (cold reset).
www.ti.com Types of Reset 10.3 Types of Reset 10.3.1 Power-On Reset (POR) Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test and emulation logic. Power-on reset is also referred to as a cold reset, since the device usually goes through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. The following steps describe the POR sequence: 1.
Types of Reset www.ti.com 10.3.3 Maximum (Max) Reset A Maximum (Max) reset is initiated by the emulator or the watchdog timer (Timer2). The effects are the same as a Warm reset, except the device boot and configuration pins are not relatched. The emulator initiates a Max reset via the ICEPICK module. This ICEPICK-initiated reset is nonmaskable. When the watchdog timer counter reaches zero, this also initiates a Max reset to recover from a runaway condition.
Default Device Configurations www.ti.com 10.3.7 Test and Emulation Reset (TRST pin) This is the Test reset on JTAG interface. Drive the TRST pin low to keep the test and emulation logic in reset. TRST needs to be released (pulled high) whenever it is necessary to use a JTAG controller to debug the device. You can pull the TRST pin high on the board if emulation is required. 10.4 Default Device Configurations After POR, Warm reset, and Max reset, the chip is in its default configuration.
Default Device Configurations www.ti.com Table 10-3. Boot Configuration Register (BOOTCFG) Field Descriptions Bit Field 31-18 Reserved 17 16 Value Description 0 DSP_BT Reserved 8 CS2_BW 7-4 Reserved 3-0 BOOTMODE Reserved. Read returns 0. DSP Boot. This bit causes the DSP to be released from reset automatically. The C64x+ boots from EMIFA (default DSPBOOTADDR address 0x4220 0000). If BOOTMODE = 2h or 3h, or PCIEN = 1, then the C64x+ self-boot will fail since EMIFA will be disabled.
Default Device Configurations www.ti.com 10.4.3 ARM Boot Mode Configuration The device configuration pins (BTMODE[3:0]) determine whether the ARM boots from its ROM or from the asynchronous EMIF (EMIFA). When ROM boot is selected (BTMODE[3:0] != 0100), a jump to the internal TCM ROM (0000 8000h) is forced into the first fetched instruction word.
Default Device Configurations www.ti.com 10.4.4 EMIFA Configuration 10.4.4.1 EMIFA CS2 Bus Width Configuration The CS2BW pin determines the default width of the first EMIFA chip select space (EM_CS2). If CS2BW = 0, the space defaults to 8-bits wide; if CS2BW = 1, the space defaults to 16-bits wide. This allows the ARM to make full use of the width of the attached memory device, if booting from EMIFA or NAND.
Default Device Configurations www.ti.com 10.4.6 DSP Boot Mode (DSP_BT) Configuration The DSP_BT input determines the DSP operation at reset. For most applications, the ARM is the master device and controls the reset and boot of the DSP. Under this scenario (DSP_BT = 0), the C64x+ DSP remains disabled (held in reset) after reset. The ARM is responsible for releasing the DSP from reset.
Reset SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 11 SPRUEP9A – May 2008 Boot Modes The TMS320DM646x DMSoC ARM can boot either from asynchronous EMIF/NOR Flash or from ARM ROM, as determined by the device configuration pins (BTMODE[3:0], CS2_BW, PCIEN, and DSP_BT) at reset. The PCIEN pin configuration is used to select the default configuration of the EMIFA/PCI/HPI pins at reset. This allows the DM646x DMSoC to be PCI-compliant at reset.
Boot Modes SPRUEP9A – May 2008 Submit Documentation Feedback
Chapter 12 SPRUEP9A – May 2008 ARM-DSP Integration Topic .................................................................................................. 12.1 12.2 12.3 12.4 12.5 Introduction ............................................................................ Shared Peripherals .................................................................. Shared Memory ....................................................................... ARM-DSP Interrupts..............................................
Introduction www.ti.com 12.1 Introduction The TMS320DM646x DMSoC integrates an ARM core for overall system control functions and a DSP subsystem for complex data and image/video processing functions. Figure 12-1 shows the interconnections between the ARM and the DSP cores and the shared resources. Both the ARM and the DSP have access to the EDMA, McASP, Timer0, and Timer1 peripherals.
Shared Peripherals www.ti.com Figure 12-1.
Shared Memory www.ti.com 12.3 Shared Memory The DM646x DMSoC memory-map is described in detail in Chapter 4. As noted in Chapter 4, ARM, DSP, and EDMA all have access to ARM internal memory, DSP internal memory, and external memory of the DDR2 memory controller and EMIFA. The EDMA can transfer data among shared memory without ARM or DSP intervention. See the TMS320DM646x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (SPRUEQ5) for more information on the EDMA. 12.3.
ARM-DSP Interrupts www.ti.com 12.4 ARM-DSP Interrupts The ARM can interrupt the DSP; conversely, the DSP can interrupt the ARM. These interrupts are generally used to allow the ARM and the DSP to coordinate. For example, the ARM may interrupt the DSP when it is ready to have the DSP process some data buffer in shared memory.
ARM Control of DSP Boot, Clock, and Reset www.ti.com 12.5 ARM Control of DSP Boot, Clock, and Reset As system master, the ARM can control all of the following functions: • Boot the DSP • Turn the clock on/off • Reset the DSP To initiate these operations, firmware on the ARM must coordinate with the DSP and use the power and sleep controller (PSC) module. This section provides specific details on how to initiate these operations.
ARM Control of DSP Boot, Clock, and Reset www.ti.com 12.5.2 DSP Module Clock ON/OFF 12.5.2.1 DSP Module Clock On In the clock enable state, the DSP’s module clock is enabled while the DSP module reset is deasserted. This is the state for normal DSP run-time. • ARM: Enable clocks to the DSP: 1. Wait for the GOSTAT[0] bit in the power domain transition status register (PTSTAT) in the PSC to clear to 0.
ARM Control of DSP Boot, Clock, and Reset www.ti.com 12.5.2.2 DSP Module Clock Off In the clock disable state, the DSP’s module clock is disabled while the DSP module reset remains deasserted. This state is typically used to disable the DSP clock to save power. • ARM: Notify the DSP to prepare for power-down. • DSP: Prepare for power-down: 1.
ARM Control of DSP Boot, Clock, and Reset www.ti.com 12.5.3.2 DSP Module Reset 12.5.3.2.1 Software Reset Disable In the software reset disable state, the DSP’s module reset is asserted and its module clock is turned off. You can use this state to reset the DSP. The following steps describe how to put the DSP in the software reset disable state: • ARM: Notify the DSP to prepare for power-down. • DSP: Put the DSP in the IDLE state: 1.
ARM Control of DSP Boot, Clock, and Reset www.ti.com 12.5.3.2.2 Synchronous Reset In the synchronous reset state, the DSP’s module reset is asserted and its module clock is enabled. You can use this state to reset the DSP. The following steps describe how to put the DSP in the synchronous reset state: • ARM: Notify the DSP to prepare for power-down. • DSP: Put the DSP in the IDLE state: 1. Set the power-down command register (PDCCMD) in the DSP power-down controller (PDC) module to 0001 5555h.
Appendix A SPRUEP9A – May 2008 Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Section 4.2.2 Additions/Modifications/Deletions Changed EMIF to EMIFA. Deleted Device Clocking chapter and renumbered subsequent chapters. Figure 5-1 Changed figure. Section 5.3 Changed first paragraph. Chapter 6 Added Chapter. Chapter 7 Added Chapter. Table 9-1 Renamed EDMA to EDMA3. Table 9-2 Renamed EDMA to EDMA3.
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