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8-5 Interrupt Request Status Register 0 (IRQ0) Field Descriptions ...................................................... 93
8-6 Interrupt Request Status Register 1 (IRQ1) Field Descriptions ...................................................... 93
8-7 Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions .................................. 94
8-8 Interrupt Request Entry Address Register (IRQENTRY) Field Descriptions ....................................... 94
8-9 Interrupt Enable Register 0 (EINT0) Field Descriptions ............................................................... 95
8-10 Interrupt Enable Register 1 (EINT1) Field Descriptions ............................................................... 95
8-11 Interrupt Operation Control Register (INTCTL) Field Descriptions .................................................. 96
8-12 Interrupt Entry Table Base Address Register (EABASE) Field Descriptions ....................................... 97
8-13 Interrupt Priority Register 0 (INTPRI0) Field Descriptions ............................................................ 98
8-14 Interrupt Priority Register 1 (INTPRI1) Field Descriptions ............................................................ 98
8-15 Interrupt Priority Register 2 (INTPRI2) Field Descriptions ............................................................ 99
8-16 Interrupt Priority Register 3 (INTPRI3) Field Descriptions ............................................................ 99
8-17 Interrupt Priority Register 4 (INTPRI4) Field Descriptions ........................................................... 100
8-18 Interrupt Priority Register 5 (INTPRI5) Field Descriptions ........................................................... 100
8-19 Interrupt Priority Register 6 (INTPRI6) Field Descriptions ........................................................... 101
8-20 Interrupt Priority Register 7 (INTPRI7) Field Descriptions ........................................................... 101
9-1 TMS320DM646x DMSoC Master IDs .................................................................................. 107
9-2 TMS320DM646x DMSoC Default Master Priorities .................................................................. 108
9-3 System Control Registers ................................................................................................ 109
10-1 Reset Types ............................................................................................................... 112
10-2 Reset Pins ................................................................................................................. 112
10-3 Boot Configuration Register (BOOTCFG) Field Descriptions ....................................................... 116
10-4 ARM Boot Configuration Register (ARMBOOT) Field Descriptions ................................................ 117
12-1 ARM-DSP Interrupt Mapping ............................................................................................ 127
12-2 DSP Boot Configuration.................................................................................................. 128
A-1 Document Revision History .............................................................................................. 133
List of Tables10 SPRUEP9A – May 2008
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