User manual

16KI$
8KD$
CP15
MMU
ARM926EJ-S
I-AHB
D-AHB
MasterI/F
16KRAM0
16KRAM1
8KROM
I-TCM
D-TCM
Slave-I/F
MasterI/F
DMA bus
ARM
interrupt
controller
(AINTC)
System
control
PLL0
PLL1
Power
sleep
controller
(PSC)
Peripherals
GFCbus
2.3 References
www.ti.com References
• Video Port Interface (VPIF)
Figure 2-1 shows the functional block diagram of the DM646x DMSoC ARM Subsystem.
The DM646x DMSoC architecture uses two primary bus subsystems to transfer data within the system:
• The DMA bus (sometimes called data bus) is used for data transfer between subsystems and
modules.
• The CFG bus (or configuration bus) is used to read/write to peripheral registers in various modules for
configuration.
Figure 2-1. TMS320DM646x DMSoC ARM Subsystem Block Diagram
See the following DM646x DMSoC related documents for more information:
• For related documentation about the DM646x DMSoC other than the ARM core, see the Related
Documentation section at the beginning of this document.
• For more detailed information about the ARM processor core, see ARM Ltd.’s web site (particularly,
see the ARM926EJ-S Technical Reference Manual):
– http://www.arm.com/documentation/ARMProcessor_Cores/index.html
SPRUEP9A – May 2008 ARM Subsystem Overview 17
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