User manual

4.2 Memory Interfaces Overview
4.2.1 DDR2 Memory Controller
4.2.2 External Memory Interface
www.ti.com Memory Interfaces Overview
• 3 Universal Asynchronous Receiver/Transmitters (UART) (one with modem control)
• Universal Serial Bus (USB) Controller
• Video Data Conversion Engine (VDCE)
• VLYNQ Interface
• 2 Video Port Interfaces (VPIF)
The ARM Subsystem also has access to the following internal peripherals:
• System Module
• PLL Controllers
• Power Sleep Controller (PSC)
• ARM Interrupt Controller (AINTC)
This section describes the different memory interfaces of DM646x DMSoC. The DM646x DMSoC supports
several memory and external device interfaces, including the following:
• DDR2 synchronous DRAM
• Asynchronous EMIF/NOR/NAND Flash
• ATA
The DDR2 memory controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A
standard compliant DDR2 SDRAM devices and can support either 16-bit or 32-bit interfaces.
DDR2 SDRAM plays a key role in a DM646x DMSoC-based system. Such a system is expected to require
a significant amount of high-speed external memory for the following:
• Buffering input image data from sensors or video sources
• Intermediate buffering for processing/resizing of image data in the video data conversion engine
(VDCE)
• Video processing display buffers
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable firmware for both the ARM and DSP
The DM646x DMSoC external memory interface (EMIF) provides an 8-bit or 16-bit data bus, an address
bus width of up to 24-bits, and 4 dedicated chip selects, along with memory control signals. These signals
are statically multiplexed between four parallel interface modules. The interface modules are:
• EMIF module - providing asynchronous EMIF (EMIFA) and NAND interfaces
• ATA – providing ATA/IDE drive support
• PCI
• HPI
Some of the control signals are configurable as GPIO signals if they are not required by the EMIFA, ATA,
PCI, and HPI. See the device-specific data manual for more information on pin multiplexing.
See the device-specific data manual for more details on pin-muxing.
SPRUEP9A – May 2008 System Memory 31
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