User manual

4.2.2.1 Asynchronous EMIF (EMIFA)
4.2.2.2 NAND (NAND, SmartMedia, xD)
4.2.2.3 ATA Controller
Memory Interfaces Overview www.ti.com
The asynchronous EMIF (EMIFA) provides both the EMIFA and NAND interfaces. Four chip selects are
provided. Each is individually configurable to provide either EMIFA or NAND support.
• The EMIFA mode supports asynchronous devices (RAM, ROM, and NOR Flash)
• 128MB asynchronous address range over 4 chip selects (32MB each)
• Supports 8-bit or 16-bit data bus widths
• Programmable asynchronous cycle timings
• Supports extended waits
• Supports Select Strobe mode
• Supports TI DSP HPI interface
• Supports booting DM646x DMSoC ARM processor from CS2 (SRAM/NOR Flash)
The asynchronous EMIF (EMIFA) provides both the EMIFA and NAND interfaces. Four chip selects are
provided and each is individually configurable to provide either EMIFA or NAND support.
• The NAND Mode supports NAND Flash on up to 4 asynchronous chip selects
• Supports 8-bit data bus width
• Programmable cycle timings
• Performs ECC calculation
• NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
• ARM ROM supports booting of the DM646x DMSoC ARM processor from NAND-Flash located at CS2
The ATA controller provides the following capabilities:
• Supports PIO, multi-word DMA, and Ultra ATA 33/44/66/100
• Supports up to mode 4 timings on PIO mode
• Supports up to mode 2 timings on multi-word DMA
• Supports up to mode 5 timings on Ultra ATA
• Full scatter gather DMA capability
• Single channel capable of connecting up to two ATA/ATAPI devices
• Programmable timing features enable timing parameters to be reprogrammed to support any ATA
timing mode at any clock frequency
Additionally, the Host IDE Controller supports multi-word DMA and Ultra DMA data transfers between
external IDE/ATAPI devices and a system memory bus interface. The timing and control registers in this
core are compatible to the Intel register set in the PIIX family.
This core has a full scatter gather DMA capability, which is compatible with the Intel scatter gather DMA
function on the PIIX chipset.
32 System Memory SPRUEP9A – May 2008
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