User manual

PLL Controller1
PLLDIV1(/1Prog)
SYSCLK1
PLLDIV2(/2Prog)
SYSCLK2
PLLDIV3(/4Prog)
SYSCLK3
PLLDIV4(/6Prog)
SYSCLK4
PLLDIV9(/6Prog)
SYSCLK9
PLLDIV5(/8Prog)
SYSCLK5
PLLDIV6(/8Prog)
SYSCLK6
PLLDIV8(/8Prog)
SYSCLK8
BPDIV(/1Prog)
SYSCLKBP
AUXCLK
DEV_MXI/
DEV_CLKIN
(27MHz)
DSP Subsystem
PCI
VDCE
HDVICP0
HDVICP1
EDMA3
Crossbar/SCR
ARMSubsystem
GPIO
Timer0
Timer1
Timer2(WD)
I2C
PWM(x2)
HPI
EMAC/MDIO
EMIFA
VLYNQ
SPI
ARMINTC
ATA
TINP0L
TINP0U
TINP1L
USB2.0
60MHz
USBPHY
UART0
McASP0
McASP1
AUX_MXI/
AUX_CLKIN
(24/48MHz)
ClockSelect
Logic
TSIF0
TSIF1
VideoPort
I/F
CLKOUT0
AUDIO_CLK0
AUDIO_CLK1
CRGEN0
CRGEN1
DDR2MemCltr
UART1
UART2
VP_CLKIN0
VP_CLKIN1
VP_CLKIN2
VP_CLKIN3
STC_CLKIN
CRG0_VCXI
CRG1_VCXI
PLLDIV1(/1Prog)
PLL Controller2
PLL2_SYSCLK1
PLLM
www.ti.com PLL Module
Figure 5-1. PLL1 and PLL2 Clock Domain Block Diagram
SPRUEP9A – May 2008 PLL Controller 37
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