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5.4.3 PLL Control Register (PLLCTL) ................................................................................. 47
5.4.4 PLL Multiplier Control Register (PLLM) ........................................................................ 48
5.4.5 PLL Controller Divider 1 Register (PLLDIV1) .................................................................. 49
5.4.6 PLL Controller Divider 2 Register (PLLDIV2) .................................................................. 50
5.4.7 PLL Controller Divider 3 Register (PLLDIV3) .................................................................. 51
5.4.8 Bypass Divider Register (BPDIV) ............................................................................... 52
5.4.9 PLL Controller Command Register (PLLCMD) ................................................................ 52
5.4.10 PLL Controller Status Register (PLLSTAT) ................................................................... 53
5.4.11 PLL Controller Clock Align Control Register (ALNCTL) ..................................................... 54
5.4.12 PLLDIV Ratio Change Status Register (DCHANGE) ........................................................ 55
5.4.13 Clock Enable Control Register (CKEN) ....................................................................... 57
5.4.14 Clock Status Register (CKSTAT) .............................................................................. 58
5.4.15 SYSCLK Status Register (SYSTAT) ........................................................................... 59
5.4.16 PLL Controller Divider n Registers (PLLDIV4-PLLDIV6, PLLDIV8, PLLDIV9) ........................... 60
6 Power and Sleep Controller (PSC) .............................................................................. 61
6.1 Introduction .................................................................................................................. 62
6.2 Power Domain and Module Topology ................................................................................... 63
6.2.1 Power Domain States ............................................................................................. 65
6.2.2 Module States ..................................................................................................... 65
6.2.3 DSP Local Reset .................................................................................................. 65
6.3 Executing Module State Transitions ..................................................................................... 66
6.4 IcePick Emulation Support in the PSC .................................................................................. 66
6.5 PSC Interrupts .............................................................................................................. 67
6.5.1 Interrupt Events .................................................................................................... 67
6.5.2 Interrupt Register Bits ............................................................................................. 68
6.5.3 Interrupt Handling ................................................................................................. 68
6.6 PSC Registers .............................................................................................................. 69
6.6.1 Peripheral Revision and Class Information Register (PID) .................................................. 70
6.6.2 Interrupt Evaluation Register (INTEVAL) ....................................................................... 70
6.6.3 Module Error Pending Register 0 (MERRPR0) ............................................................... 71
6.6.4 Module Error Pending Register 1 (MERRPR1) ............................................................... 71
6.6.5 Module Error Clear Register 0 (MERRCR0) ................................................................... 72
6.6.6 Module Error Clear Register 1 (MERRCR1) ................................................................... 72
6.6.7 Power Domain Transition Command Register (PTCMD) .................................................... 73
6.6.8 Power Domain Transition Status Register (PTSTAT) ........................................................ 73
6.6.9 Power Domain Status Register (PDSTAT0) ................................................................... 74
6.6.10 Power Domain Control Register (PDCTL0) ................................................................... 75
6.6.11 Module Status n Register (MDSTAT0-MDSTAT45) ......................................................... 76
6.6.12 Module Control n Register (MDCTL0-MDCTL45) ............................................................ 77
7 Power Management .................................................................................................. 79
7.1 Overview..................................................................................................................... 80
7.2 PSC and PLLC Overview ................................................................................................. 80
7.3 Clock Management ........................................................................................................ 81
7.3.1 Module Clock ON/OFF ........................................................................................... 81
7.3.2 Module Clock Frequency Scaling ............................................................................... 81
7.3.3 PLL Bypass and Power Down ................................................................................... 81
7.4 ARM and DSP Sleep Mode Management .............................................................................. 81
7.4.1 ARM Wait-For-Interrupt Sleep Mode ........................................................................... 81
4 Contents SPRUEP9A – May 2008
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