User manual

5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset
5.3.2.2 Initialization to PLL Mode from PLL Power Down
www.ti.com PLL2 Control
This section discusses the steps to change the PLL2 frequency when the DDR2 memory controller is
already out of reset.
1. Stop DDR2 memory controller accesses and purge any outstanding requests.
2. Put the DDR2 memory in self-refresh mode and stop the DDR2 memory controller clock. The DDR2
memory controller clock shut down sequence is in the TMS320DM646x DMSoC DDR2 Memory
Controller User's Guide (SPRUEQ4 ).
3. Program the PLL2 clocks by following the steps in the appropriate section: Section 5.3.2.2 ,
Section 5.3.2.3 , or Section 5.3.2.4 . (Discussion in Section 5.3.2 explains which is the appropriate
subsection).
4. Re-enable the DDR2 memory controller clock. The DDR2 memory controller clock on sequence is in
the TMS320DM646x DMSoC DDR2 Memory Controller User's Guide (SPRUEQ4 ).
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow this procedure to change PLL2
frequencies.
1. Select the clock mode by programming the CLKMODE bit in PLLCTL.
2. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 20 MXI clock cycles to ensure PLLC switches to bypass mode properly.
3. Set the PLLRST bit in PLLCTL to 1 (reset PLL)
4. Set the PLLDIS bit in PLLCTL to 1 (disable PLL output).
5. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
6. Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that
the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to
the rest of the device.
7. Wait for PLL stabilization time. (4096 MXI clock cycles)
8. Program the required multiplier value in the PLL multiplier control register (PLLM).
9. If necessary, program the PLL controller divider 1 register (PLLDIV1) to change the SYSCLK1 divide
value:
a. Program the RATIO field in PLLDIV1 with the desired divide factor.
b. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
c. Wait for the GOSTAT bit in the PLL controller status register (PLLSTAT) to clear to 0 (completion of
phase alignment).
10. Wait for PLL to reset properly. The PLL reset time is a minimum of 32 MXI clock cycles.
11. Clear the PLLRST bit in PLLCTL to 0 to bring the PLL out of reset.
12. Wait for 2000 MXI clock or reference clock cycles to allow PLL to lock.
13. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
For information on initializing the DDR2 memory controller, see the TMS320DM646x DMSoC DDR2
Memory Controller User's Guide (SPRUEQ4 ).
SPRUEP9A – May 2008 PLL Controller 43
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