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5.4.5 PLL Controller Divider 1 Register (PLLDIV1)
www.ti.com PLL Controller Register Map
The PLL controller divider 1 register (PLLDIV1) is shown in Figure 5-8 and described in Table 5-9 .
Divider 1 controls the divider for SYSCLK1.
Note: On the DM646x DMSoC, all PLL1 SYSCLK n dividers are programmable but you should not
change the divider value to maintain the clock ratios between various modules of the device.
You should only use the power-up default divider values for all PLL1 SYSCLK n dividers for
normal device operation.
PLL2 SYSCLK1 divider value is programmable and you may change the divider value for the
desired DDR2 memory controller clock frequency.
Figure 5-8. PLL Controller Divider 1 Register (PLLDIV1)
31 16
Reserved
R-0
15 14 4 3 0
D1EN Reserved RATIO
R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 5-9. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 D1EN Divider enable for SYSCLK1.
0 Disable
1 Enable
14-4 Reserved 0 Reserved
3-0 RATIO 0-Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
SPRUEP9A – May 2008 PLL Controller 49
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