User manual

5.4.7 PLL Controller Divider 3 Register (PLLDIV3)
www.ti.com PLL Controller Register Map
The PLL controller divider 3 register (PLLDIV3) is shown in Figure 5-10 and described in Table 5-11 .
Divider 3 controls the divider for SYSCLK3. PLLDIV3 is not used on PLL2.
Note: On the DM646x DMSoC, all PLL1 SYSCLK n dividers are programmable but you should not
change the divider value to maintain the clock ratios between various modules of the device.
You should only use the power-up default divider values for all PLL1 SYSCLK n dividers for
normal device operation.
Figure 5-10. PLL Controller Divider 3 Register (PLLDIV3)
31 16
Reserved
R-0
15 14 4 3 0
D3EN Reserved RATIO
R/W-1 R-0 R/W-3h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 5-11. PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 D3EN Divider enable for SYSCLK3.
0 Disable
1 Enable
14-4 Reserved 0 Reserved
3-0 RATIO 0-Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 3h (PLL divide by 4).
SPRUEP9A – May 2008 PLL Controller 51
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