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5.4.10 PLL Controller Status Register (PLLSTAT)
www.ti.com PLL Controller Register Map
The PLL controller status register (PLLSTAT) is shown in Figure 5-13 and described in Table 5-14 .
Figure 5-13. PLL Controller Status Register (PLLSTAT)
31 16
Reserved
R-0
15 3 2 1 0
Reserved STABLE Reserved GOSTAT
R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 5-14. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2 STABLE OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0 No
1 Yes
1 Reserved 0 Reserved
0 GOSTAT Status of GO operation. If 1, indicates GO operation is in progress.
0 GO operation is not in progress.
1 GO operation is in progress.
SPRUEP9A – May 2008 PLL Controller 53
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