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PLL Controller Register Map www.ti.com
Table 5-16. PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions (continued)
Bit Field Value Description
3 SYS4 SYSCLK4 divide ratio is modified. SYSCLK4 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK4 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK4 changes to the new divide ratio.
2 SYS3 SYSCLK3 divide ratio is modified. SYSCLK3 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK3 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK3 changes to the new divide ratio.
1 SYS2 SYSCLK2 divide ratio is modified. SYSCLK2 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK2 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK2 changes to the new divide ratio.
0 SYS1 SYSCLK1 divide ratio is modified. SYSCLK1 divide ratio is changed during GO operation.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK1 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK1 changes to the new divide ratio.
PLL Controller56 SPRUEP9A – May 2008
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