User manual

6.1 Introduction
armclock
armmodulereset
armpower
AINTC
ARM
dspclock
dspmodulereset
dsplocalreset
DSP
dsppower
peripheralclock
peripheralmodulereset
MODx
peripheralpower
Alwayson
domain
Interrupt
PSC
PLLC
clks
VDD
RESET
Emulation
Introduction www.ti.com
In the TMS320DM646x DMSoC system, the Power and Sleep Controller (PSC) is responsible for
managing transitions of clock on/off and reset. A block diagram of the PSC is shown in Figure 6-1 . Many
of the PSC operations are transparent to software, such as hard reset operations. However, the PSC
provides you with an interface to control several important clock and reset operations. The clock and reset
operations are described in this chapter.
The PSC includes the following features:
• Manages chip resets
• Provides a software interface to:
– Control module clock ON/OFF
– Control module resets
– Control DSP local reset (CPU reset)
• Supports IcePick emulation features: power, clock, and reset
Figure 6-1. TMS320DM646x DMSoC Power and Sleep Controller (PSC)
62 Power and Sleep Controller (PSC) SPRUEP9A – May 2008
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