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Power Domain and Module Topology

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Table 6-1. Module Configuration

Default State

Module Module State

Number Module Name [STATE bit in MDSTAT n in PSC] Local Reset State

0 Reserved Reserved -

1 DSP C64x+ If DSPBOOT = 0, SwRstDisable DSPBOOT

If DSPBOOT = 1, Enable

2 HDVICP0 SwRstDisable -

3 HDVICP1 SwRstDisable -

4 EDMA3CC SwRstDisable -

5 EDMA3TC0 SwRstDisable -

6 EDMA3TC1 SwRstDisable -

7 EDMA3TC2 SwRstDisable -

8 EDMA3TC3 SwRstDisable -

9 USB2.0 SwRstDisable -

10 ATA SwRstDisable -

11 VLYNQ SwRstDisable -

12 HPI SwRstDisable -

13 PCI SwRstDisable -

14 EMAC/MDIO SwRstDisable -

15 VDCE SwRstDisable -

16 Video Port 0 SwRstDisable -

17 Video Port 1 SwRstDisable -

18 TSIF0 SwRstDisable -

19 TSIF1 SwRstDisable -

20 DDR2 Memory Contoller SwRstDisable -

21 EMIFA If BTMODE[3:0] ≠ 0100, SwRstDisable -

If BTMODE[3:0] = 0100, Enable

22 McASP0 SwRstDisable -

23 McASP1 SwRstDisable -

24 CRGEN0 SwRstDisable -

25 CRGEN1 SwRstDisable -

26 UART0 SwRstDisable -

27 UART1 SwRstDisable -

28 UART2 SwRstDisable -

29 PWM0 SwRstDisable -

30 PWM1 SwRstDisable -

31 I2C SwRstDisable -

32 SPI SwRstDisable -

33 GPIO SwRstDisable -

34 Timer0 SwRstDisable -

35 Timer1 SwRstDisable -

36-44 Reserved Reserved -

45 ARM INTC Enable -

Power and Sleep Controller (PSC)64 SPRUEP9A – May 2008

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