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6.2.1 Power Domain States
6.2.2 Module States
6.2.3 DSP Local Reset
www.ti.com Power Domain and Module Topology
A power domain can only be in one of two states: ON or OFF, defined as:
• ON: power to the power domain is on.
• OFF: power to the power domain is off.
In the DM646x DMSoC, there is only one power domain (Always On) .The Always On power domain is
always in the ON state when the chip is powered-on.
A module can be in one of four states: Disable, Enable, SyncReset, or SwRstDisable, as defined by the
STATE bit in the module status n register (MDSTAT n) in the PSC. These four states correspond to
combinations of module reset asserted or deasserted and module clock on or off, as shown in Table 6-2 .
Note: Module Reset is defined to completely reset a given module, so that all hardware returns to
its default state. See Chapter 10 for more information on module reset.
For more information on the DM646x DMSoC power management, see Chapter 7 .
Table 6-2. Module States
Module State Module Reset Module Clock Module State Definition
Enable Deasserted On A module in the Enable state has its module reset deasserted and it
has its clock on. This is the normal run-time state for a given module.
Disable Deasserted Off A module in the Disable state has its module reset deasserted and it
has its clock off. This state is typically used for disabling a module
clock to save power. The DM646x DMSoC is designed in full static
CMOS, so when you stop a module clock, it retains the module's state.
When the clock is restarted, the module resumes operating from the
stopping point.
SyncReset Asserted On A module in the SyncReset state has its module reset asserted and it
has its clock on. After initial power-on, most modules are in the
SyncRst state by default (see Table 6-1 ). Generally, software is not
expected to initiate this state.
SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted
and it has its clock set to off. Generally, software is not expected to
initiate this state.
In addition to module reset (as described in Section 6.2.2 ), the DSP CPU can be reset using a special
local reset. When DSP local reset is asserted, the DSP’s internal memories (L1P, L1D, and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of the DSP subsystem, as would
the DSP module reset. Local reset is useful when the DSP module is in the Enable state or in the Disable
state; since module reset is asserted in the SyncReset and SwRstDisable states, and module reset takes
precedence over local reset. The ARM uses local reset to reset the DSP to initiate the DSP boot process.
See Chapter 10 and Chapter 12 for more information on local reset, as well as DSP boot.
The procedures for asserting and deasserting DSP local reset are:
1. Clear the LRST bit in the module control 1 register (MDCTL1) in the PSC to 0. This asserts the DSP
local reset. By default, after power-on reset or hard reset, the DSP boot source (DSPBOOT) pin
determines the default state of the LRST bit in MDCTL1. See Chapter 10 for more information on this
boot configuration pin.
2. Set the LRST bit in MDCTL1 to 1. This deasserts the DSP local reset. After reset is deasserted, if the
DSP is in the Enable state, the DSP immediately begins code execution from the boot address
programmed in the DSP boot address register (DSPBOOTADDR) in the System Module.
SPRUEP9A – May 2008 Power and Sleep Controller (PSC) 65
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