User manual

6.6 PSC Registers
www.ti.com PSC Registers
Table 6-6 lists the memory-mapped registers for the PSC. See the device-specific data manual for the
memory address of these registers.
Table 6-6. Power and Sleep Controller (PSC) Registers
Offset Register Description Section
0h PID Peripheral Revision and Class Information Register Section 6.6.1
18h INTEVAL Interrupt Evaluation Register Section 6.6.2
40h MERRPR0 Module Error Pending Register 0 (modules 0-31) Section 6.6.3
44h MERRPR1 Module Error Pending Register 1 (modules 32-45) Section 6.6.4
50h MERRCR0 Module Error Clear Register 0 (modules 0-31) Section 6.6.5
54h MERRCR1 Module Error Clear Register 1 (modules 32-45) Section 6.6.6
120h PTCMD Power Domain Transition Command Register Section 6.6.7
128h PTSTAT Power Domain Transition Status Register Section 6.6.8
200h PDSTAT0 Power Domain Status Register Section 6.6.9
300h PDCTL0 Power Domain Control Register Section 6.6.10
800h MDSTAT n Module Status n Register (modules 0-45) Section 6.6.11
A00h MDCTL n Module Control n Register (modules 0-45) Section 6.6.12
SPRUEP9A – May 2008 Power and Sleep Controller (PSC) 69
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