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6.6.10 Power Domain Control Register (PDCTL0)
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The power domain control register (PDCTL0) is shown in Figure 6-12 and described in Table 6-16 .
Figure 6-12. Power Domain Control Register (PDCTL0)
31 16
Reserved
R-0
15 10 9 8 7 1 0
Reserved Reserved Reserved NEXT
R-0 R/W-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 6-16. Power Domain Control Register (PDCTL0) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reserved
9-8 Reserved 0 Reserved. Always write 0 to these bits.
7-1 Reserved 0 Reserved
0 NEXT Power domain next state. In the DM646x DMSoC, there is only one power domain (Always On) .The
Always On power domain is always in the ON state when the chip is powered-on. This field has no
effect.
0 Power domain off.
1 Power domain on.
SPRUEP9A – May 2008 Power and Sleep Controller (PSC) 75
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