User manual

7.5 I/O Management
7.5.1 3.3 V I/O Power-Down
7.6 USB Phy Power Down
www.ti.com I/O Management
The 3.3 V I/O drivers are fabricated out of 1.8 V transistors with design techniques that require a DC bias
current. These I/O cells have a power-down mode that turns off the DC current. The VDD3P3V_PWDN
register in the System Module controls power to the 3.3V I/O cells. The 3.3V I/Os are separated into
functional groups for independent control different modules. For these groups, only the I/O cells needed
for Host/AEMIF boot or power up operations are powered up by default (CLKOUT, boot configuration pins,
PCI/HPI/AEMIF Blocks, GPIO Block). All other I/O cells are powered down by default to save power.
Note: If any of these I/O pins are needed for the application, be sure that application code starts
out by programming the corresponding bits in VDD3P3V_PWDN to 0 to power up the I/O
cells.
See the device-specific data manual for details on the VDD3P3V_PWDN register.
You can power-down the USB Phy peripheral when it is not in use. The USB Phy is powered-down via the
PHYPDWN bit in the USBCTL register of the system control module. USBCTL is described in the
device-specific data manual.
SPRUEP9A – May 2008 Power Management 83
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