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Table 8-1. ARM Interrupt Map
ARM ARM
Interrupt Interrupt
Number Acronym Source Number Acronym Source
0 VP_VERTINT0 VPIF 32 TINTL0 Timer 0 lower – TINT12
1 VP_VERTINT1 VPIF 33 TINTH0 Timer 0 upper – TINT34
2 VP_VERTINT2 VPIF 34 TINTL1 Timer 1 lower – TINT12
3 VP_VERTINT3 VPIF 35 TINTH1 Timer 1 upper – TINT34
4 VP_ERRINT VPIF 36 PWMINT0 PWM 0
5 - Reserved 37 PWMINT1 PWM 1
6 - Reserved 38 VLQINT VLYNQ
7 WDINT WD Timer (TIMER 2) – 39 I2CINT I2C
TINT12
8 CRGENINT0 CRGEN 0 40 UARTINT0 UART 0
9 CRGENINT1 CRGEN 1 41 UARTINT1 UART 1
10 TSINT0 TSIF 0 42 UARTINT2 UART 2
11 TSINT1 TSIF 1 43 SPINT0 SPI
12 VDCEINT VDCE 44 SPINT1 SPI
13 USBINT USB 45 DSP2ARM0 DSP Controller to ARM
14 USBDMAINT USB DMA 46 - Reserved
15 PCIINT PCI 47 PSCINT Power and Sleep
Controller
16 CCINT0 EDMA CC Region 0 48 GPIO0 GPIO
17 CCERRINT EDMA CC Error 49 GPIO1 GPIO
18 TCERRINT0 EDMA TC 0 Error 50 GPIO2 GPIO
19 TCERRINT1 EDMA TC 1 Error 51 GPIO3 GPIO
20 TCERRINT2 EDMA TC 2 Error 52 GPIO4 GPIO
21 TCERRINT3 EDMA TC 3 Error 53 GPIO5 GPIO
22 IDEINT ATA 54 GPIO6 GPIO
23 HPIINT HPI 55 GPIO7 GPIO
24 MAC_RXTH EMAC Receive 56 GPIOBNK0 GPIO Bank 0
Threshold
25 MAC_RX EMAC Receive 57 GPIOBNK1 GPIO Bank 1
26 MAC_TX EMAC Transmit 58 GPIOBNK2 GPIO Bank 2
27 MAC_MISC EMAC Miscellaneous 59 DDRINT DDR2 Memory Controller
28 AXINT0 McASP0 Transmit 60 EMIFAINT EMIFA
29 ARINT0 McASP0 Receive 61 COMMTX ARMSS
30 AXINT1 McASP1 Transmit 62 COMMRX ARMSS
31 - Reserved 63 EMUINT E2ICE
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 87
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