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8.3.2 Interrupt Prioritization
8.3.3 Vector Table Entry Address Generation
ReturnfromINTEABASE
InterruptentrytableAddress
BranchtoINTEABASE+(1*SIZE)
BranchtoINT1EABASE+(2*SIZE)
BranchtoINT63EABASE+(64*SIZE)
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AINTC Methodology
Event priority is determined using both a fixed and a programmable prioritization scheme. The AINTC has
8 different programmable interrupt priorities. Priority 0 and priority 1 are mapped to the FIQ interrupt with
priority 0 being the highest priority. Priorities 2-7 are mapped to the IRQ interrupt (priority 2 is the highest,
priority 7 is the lowest). Each interrupt is mapped to a priority level using the INTPRIn registers. When
simultaneous events occur (multiple enabled events captured in IRQ or FIQ registers), the event with the
highest priority is the one whose entry table address is generated when sending the interrupt signal to the
ARM. When events of identical priority occur, the event with the lowest event number is treated as having
the higher priority.
To help speed up the ISR, the AINTC provides two vectors into the ARM’s interrupt entry table, which
correspond to the highest priority effective IRQ and FIQ interrupts. This vector is generated by modifying a
base address with a priority index. The priority index takes the size of each interrupt entry into account
using the following formulas:
IRQENTRY = EABASE + ((highest priority IRQ EVT# + 1) × SIZE)
FIQENTRY = EABASE + ((highest priority FIQ EVT# + 1) × SIZE)
The EABASE base address is contained in a register. The SIZE value is a programmable register field,
which selects 4, 8, 16, or 32 bytes for each interrupt table entry. The IRQENTRY or FIQENTRY register is
read by the ARM, depending on which type of interrupt it is servicing. The ARM interrupt entry table format
is shown in Figure 8-2 .
Figure 8-2. Interrupt Entry Table
The highest priority effective IRQ or FIQ interrupt includes only those interrupts that are enabled by their
corresponding EINT bit by default. However, the IERAW and FERAW register bits, if set, allow the highest
priority event of any of those captured in the IRQ or FIQ register to be used in calculating IRQENTRY and
FIQENTRY, respectively (regardless of the EINT state).
The IRQENTRY and FIQENTRY values are generated in real time as the interrupt events occur. Thus,
their values may change from the time that the IRQ or FIQ is sent to the ARM to the time the ARM reads
the register. They may also change immediately after a read by the ARM if a higher priority event occurs.
If no IRQ mapped effective interrupt is pending, then the IRQENTRY value reflects the EABASE value.
Similarly, if no FIQ mapped effective interrupt is pending, then the FIQENTRY value reflects the EABASE
value.
1. For the FIQENTRY:
• If FERAW is 0, FIQENTRY reflects the state of the highest priority pending enabled FIQ interrupt. If
the active FIQ interrupt is cleared in FIQn, then FIQENTRY is immediately updated with the vector
of the next highest priority pending enabled FIQ interrupt.
• If FERAW is 1, FIQENTRY reflects the state of the highest priority pending FIQ interrupt (enabled
or not). If the active FIQ interrupt is cleared in FIQn, then FIQENTRY is immediately updated with
the vector of the next highest priority pending interrupt (enabled or not).
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 89
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