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CLK
EABASE
VECTORn
EABASE
INTn
EINTn
IRQn/FIQn
IRQz/FIQz
ENTRY
Eventpulse
Disabled
Cleared
8.4 AINTC Registers
www.ti.com AINTC Registers
Figure 8-4. Delayed Interrupt Disable
Table 8-2 lists the memory-mapped registers for the AINTC. See the device-specific data manual for the
memory address of these registers.
Table 8-2. ARM Interrupt Controller (AINTC) Registers
Offset Acronym Register Description Section
00h FIQ0 Fast Interrupt Request Status Register 0 Section 8.4.1
04h FIQ1 Fast Interrupt Request Status Register 1 Section 8.4.2
08h IRQ0 Interrupt Request Status Register 0 Section 8.4.3
0Ch IRQ1 Interrupt Request Status Register 1 Section 8.4.4
10h FIQENTRY Fast Interrupt Request Entry Address Register Section 8.4.5
14h IRQENTRY Interrupt Request Entry Address Register Section 8.4.6
18h EINT0 Interrupt Enable Register 0 Section 8.4.7
1Ch EINT1 Interrupt Enable Register 1 Section 8.4.8
20h INTCTL Interrupt Operation Control Register Section 8.4.9
24h EABASE Interrupt Entry Table Base Address Register Section 8.4.10
30h INTPRI0 Interrupt 0-7 Priority Register 0 Section 8.4.11
34h INTPRI1 Interrupt 8-15 Priority Register 1 Section 8.4.12
38h INTPRI2 Interrupt 16-23 Priority Register 2 Section 8.4.13
3Ch INTPRI3 Interrupt 24-31 Priority Register 3 Section 8.4.14
40h INTPRI4 Interrupt 32-39 Priority Register 4 Section 8.4.15
44h INTPRI5 Interrupt 40-47 Priority Register 5 Section 8.4.16
48h INTPRI6 Interrupt 48-55 Priority Register 6 Section 8.4.17
4Ch INTPRI7 Interrupt 56-63 Priority Register 7 Section 8.4.18
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 91
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