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8.4.3 Interrupt Request Status Register 0 (IRQ0)
8.4.4 Interrupt Request Status Register 1 (IRQ1)
www.ti.com AINTC Registers
The interrupt request status register 0 (IRQ0) is shown in Figure 8-7 and described in Table 8-5 . Interrupt
status of INT[31:0] (if mapped to IRQ).
Figure 8-7. Interrupt Request Status Register 0 (IRQ0)
31 16
IRQ
R/W-1
15 1 0
IRQ IRQ0
R/W-1 R-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-5. Interrupt Request Status Register 0 (IRQ0) Field Descriptions
Bit Field Value Description
31-1 IRQ[ n] Interrupt status of INT n, if mapped to interrupt request (IRQ31-1).
0 When reading bit, interrupt occurred.
1 When writing bit, acknowledge interrupt.
0 IRQ0 1 Interrupt 0 is always mapped to fast interrupt request (FIQ).
The interrupt request status register 1 (IRQ1) is shown in Figure 8-8 and described in Table 8-6 . Interrupt
status of INT[63:32] (if mapped to IRQ).
Figure 8-8. Interrupt Request Status Register 1 (IRQ1)
31 16
Reserved
R-1
15 0
IRQ
R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-6. Interrupt Request Status Register 1 (IRQ1) Field Descriptions
Bit Field Value Description
31-16 Reserved 1 Reserved
15-0 IRQ[ n] Interrupt status of INT n, if mapped to fast interrupt request (IRQ47-32).
0 When reading bit, interrupt occurred.
1 When writing bit, acknowledge interrupt.
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 93
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