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8.4.7 Interrupt Enable Register 0 (EINT0)
8.4.8 Interrupt Enable Register 1 (EINT1)
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The interrupt enable register 0 (EINT0) is shown in Figure 8-11 and described in Table 8-9 .
Figure 8-11. Interrupt Enable Register 0 (EINT0)
31 16
EINT
R/W-0
15 1 0
EINT EINT0
R/W-0 R-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-9. Interrupt Enable Register 0 (EINT0) Field Descriptions
Bit Field Value Description
31-1 EINT[ n] Interrupt enable for INT n. Bits 1 through 31 represent interrupts 1-31, respectively.
0 Interrupt is disabled.
1 Interrupt is enabled.
0 EINT0 1 Interrupt 0 is nonmaskable and is always enabled.
The interrupt enable register 1 (EINT1) is shown in Figure 8-12 and described in Table 8-10 .
Figure 8-12. Interrupt Enable Register 1 (EINT1)
31 16
Reserved
R-0
15 0
EINT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-10. Interrupt Enable Register 1 (EINT1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15-0 EINT[ n] Interrupt enable for INT n. Bits 0 through 15 represent interrupts 32-47, respectively.
0 Interrupt is disabled.
1 Interrupt is enabled.
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 95
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