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8.4.9 Interrupt Operation Control Register (INTCTL)
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The interrupt operation control register (INTCTL) is shown in Figure 8-13 and described in Table 8-11 .
Figure 8-13. Interrupt Operation Control Register (INTCTL)
31 16
Reserved
R-0
15 3 2 1 0
Reserved IDMODE IERAW FERAW
R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-11. Interrupt Operation Control Register (INTCTL) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2 IDMODE Interrupt disable mode.
0 Disable immediately.
1 Disable after acknowledgement.
1 IERAW Masked interrupt reflected in the interrupt request entry address register (IRQENTRY).
0 Disable reflect.
1 Enable reflect.
0 FERAW Masked interrupt reflect in the fast interrupt request entry address register (FIQENTRY).
0 Disable reflect.
1 Enable reflect.
ARM Interrupt Controller (AINTC)96 SPRUEP9A – May 2008
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