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8.4.10 Interrupt Entry Table Base Address Register (EABASE)
www.ti.com AINTC Registers
The interrupt entry table base address register (EABASE) is shown in Figure 8-14 and described in
Table 8-12 .
Figure 8-14. Interrupt Entry Table Base Address Register (EABASE)
31 29 28 16
Reserved EABASE
R-0 R/W-0
15 3 2 1 0
EABASE Reserved SIZE
R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-12. Interrupt Entry Table Base Address Register (EABASE) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reserved
28-3 EABASE 0-3FF FFFFh Interrupt entry table base address (8-byte aligned).
2 Reserved 0 Reserved
1-0 SIZE 0-3h Size of each entry in the interrupt entry table.
0 4 bytes
1h 8 bytes
2h 16 bytes
3h 32 bytes
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 97
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