User manual

8.4.11 Interrupt Priority Register 0 (INTPRI0)
8.4.12 Interrupt Priority Register 1 (INTPRI1)
AINTC Registers www.ti.com
The interrupt priority register 0 (INTPRI0) is shown in Figure 8-15 and described in Table 8-13 .
Figure 8-15. Interrupt Priority Register 0 (INTPRI0)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT7 Reserved INT6 Reserved INT5 Reserved INT4
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT3 Reserved INT2 Reserved INT1 Reserved INT0
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-13. Interrupt Priority Register 0 (INTPRI0) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
The interrupt priority register 1 (INTPRI1) is shown in Figure 8-16 and described in Table 8-14 .
Figure 8-16. Interrupt Priority Register 1 (INTPRI1)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT15 Reserved INT14 Reserved INT13 Reserved INT12
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT11 Reserved INT10 Reserved INT9 Reserved INT8
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-14. Interrupt Priority Register 1 (INTPRI1) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
ARM Interrupt Controller (AINTC)98 SPRUEP9A – May 2008
Submit Documentation Feedback