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8.4.13 Interrupt Priority Register 2 (INTPRI2)
8.4.14 Interrupt Priority Register 3 (INTPRI3)
www.ti.com AINTC Registers
The interrupt priority register 2 (INTPRI2) is shown in Figure 8-17 and described in Table 8-15 .
Figure 8-17. Interrupt Priority Register 2 (INTPRI2)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT23 Reserved INT22 Reserved INT21 Reserved INT20
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT19 Reserved INT18 Reserved INT17 Reserved INT16
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-15. Interrupt Priority Register 2 (INTPRI2) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
The interrupt priority register 3 (INTPRI3) is shown in Figure 8-18 and described in Table 8-16 .
Figure 8-18. Interrupt Priority Register 3 (INTPRI3)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT31 Reserved INT30 Reserved INT29 Reserved INT28
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT27 Reserved INT26 Reserved INT25 Reserved INT24
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-16. Interrupt Priority Register 3 (INTPRI3) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 99
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