Datasheet

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E –JANUARY 2000–REVISED APRIL 2013 www.ti.com
Address
Contents
(1)
S/ADD REG
xxBE UART Prescale Select Register (Reg:PSR)
xxBF Reserved for UART
xxC0 Timer T2 Lower Byte
xxC1 Timer T2 Upper Byte
xxC2 Timer T2 Autoload Register T2RA Lower Byte
xxC3 Timer T2 Autoload Register T2RA Upper Byte
xxC4 Timer T2 Autoload Register T2RB Lower Byte
xxC5 Timer T2 Autoload Register T2RB Upper Byte
xxC6 Timer T2 Control Register
xxC7 WATCHDOG Service Register (Reg:WDSVR)
xxC8 MIWU Edge Select Register (Reg:WKEDG)
xxC9 MIWU Enable Register (Reg:WKEN)
xxCA MIWU Pending Register (Reg:WKPND)
xxCB to xxCF Reserved
xxD0 Port L Data Register
xxD1 Port L Configuration Register
xxD2 Port L Input Pins (Read Only)
xxD3 Reserved for Port L
xxD4 Port G Data Register
xxD5 Port G Configuration Register
xxD6 Port G Input Pins (Read Only)
xxD7 Port I Input Pins (Read Only) (Actually reads Port F input pins)
xxD8 Port C Data Register
xxD9 Port C Configuration Register
xxDA Port C Input Pins (Read Only)
xxDB Reserved for Port C
xxDC Port D
xxDD to xxDF Reserved for Port D
xxE0 to xxE5 Reserved for EE Control Registers
xxE6 Timer T1 Autoload Register T1RB Lower Byte
xxE7 Timer T1 Autoload Register T1RB Upper Byte
xxE8 ICNTRL Register
xxE9 MICROWIRE/PLUS Shift Register
xxEA Timer T1 Lower Byte
xxEB Timer T1 Upper Byte
xxEC Timer T1 Autoload Register T1RA Lower Byte
xxED Timer T1 Autoload Register T1RA Upper Byte
xxEE CNTRL Control Register
xxEF PSW Register
xxF0 to FB On-Chip RAM Mapped as Registers
xxFC X Register
xxFD SP Register
xxFE B Register
xxFF S Register
0100–017F On-Chip 128 RAM Bytes
0200–027F On-Chip 128 RAM Bytes (Reads as undefined data on COP8SGE)
0300–037F On-Chip 128 RAM Bytes (Reads as undefined data on COP8SGE)
58 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7