Datasheet

16-Bit Buffers/Line Drivers
SCCS028B - December 1987 - Revised September 2001
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16244T
CY74FCT162244T
CY74FCT162H244T
Copyright © 2001, Texas Instruments Incorporated
1CY74FCT16444T/2
H244T
Features
•I
off
supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of –40˚C to +85˚C
• V
CC
= 5V ± 10%
CY74FCT16244T Features:
• 64 mA sink current, 32 mA source current
• Typical V
OLP
(ground bounce)
<1.0V at V
CC
= 5V, T
A
= 25˚C
CY74FCT162244T Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical V
OLP
(ground bounce)
<0.6V at V
CC
= 5V, T
A
= 25˚C
CY74FCT162H244T Features:
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 16-bit buffers/line drivers are designed for use in
memory driver, clock driver, or other bus interface applications,
where high-speed and low power are required. With
flow-through pinout and small shrink packaging board layout
is simplified. The three-state controls are designed to allow
4-bit, 8-bit or combined 16-bit operation.
This device is fully specified for partial-power-down
applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16244T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162244T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for mini-
mal undershoot and reduced ground bounce. The
CY74FCT162244T is ideal for driving transmission lines.
The CY74FCT162H244T is a 24-mA balanced output part that
has “bus hold” on the data inputs. The device retains the in-
put’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and pre-
vents floating inputs.
GND
Logic Block Diagrams CY74FCT16244T, CY74FCT162244T,
CY74FCT162H244T
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
1
OE
34
SSOP/TSSOP
Top View
1
Y
1
1
Y
2
1
Y
3
1
Y
4
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1
A
1
1
A
2
1
A
3
1
A
4
1
OE
2
Y
1
2
Y
2
2
Y
3
2
Y
4
2
A
1
2
A
2
2
A
3
2
A
4
2
OE
1
Y
1
1
Y
2
1
Y
3
1
Y
4
1
A
1
1
A
2
1
A
3
1
A
4
2
OE
GND
GND
V
CC
2
Y
3
2
Y
4
2
Y
1
2
Y
2
2
A
1
2
A
2
2
A
3
2
A
4
V
CC
GND
GND
3
Y
3
3
Y
4
3
Y
1
3
Y
2
3
A
1
3
A
2
3
A
3
3
A
4
GND
GND
V
CC
4
Y
3
4
Y
4
4
Y
1
4
Y
2
4
A
1
4
A
2
4
A
3
4
A
4
V
CC
GND
4
OE
3
OE
3
Y
1
3
Y
2
3
Y
3
3
Y
4
3
A
1
3
A
2
3
A
3
3
A
4
3
OE
4
Y
1
4
Y
2
4
Y
3
4
Y
4
4
A
1
4
A
2
4
A
3
4
A
4
4
OE
FCT16244–1 FCT16244–2
FCT16244–3
FCT16244–4
FCT16244–5
16244T
162244T
162H244T