Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) PDIP 16

DAC0800, DAC0802

www.ti.com

SNAS538C –JUNE 1999–REVISED FEBRUARY 2013

DAC0800/DAC0802 8-Bit Digital-to-Analog Converters

Check for Samples: DAC0800, DAC0802

FEATURES

DESCRIPTION

The DAC0800 series are monolithic 8-bit high-speed

• Fast Settling Output Current: 100 ns

current-output digital-to-analog converters (DAC)

• Full Scale Error: ±1 LSB

featuring typical settling times of 100 ns. When used

• Nonlinearity Over Temperature: ±0.1%

as a multiplying DAC, monotonic performance over a

40 to 1 reference current range is possible. The

• Full Scale Current Drift: ±10 ppm/°C

DAC0800 series also features high compliance

• High Output Compliance: −10V to +18V

complementary current outputs to allow differential

• Complementary Current Outputs

output voltages of 20 Vp-p with simple resistor loads.

The reference-to-full-scale current matching of better

• Interface Directly with TTL, CMOS, PMOS and

than ±1 LSB eliminates the need for full-scale trims in

Others

most applications, while the nonlinearities of better

• 2 Quadrant Wide Range Multiplying Capability

than ±0.1% over temperature minimizes system error

• Wide Power Supply Range: ±4.5V to ±18V

accumulations.

• Low Power Consumption: 33 mW at ±5V

The noise immune inputs will accept a variety of logic

• Low Cost

levels. The performance and characteristics of the

device are essentially unchanged over the ±4.5V to

±18V power supply range and power consumption at

only 33 mW with ±5V supplies is independent of logic

input levels.

The DAC0800, DAC0802, DAC0800C and

DAC0802C are a direct replacement for the DAC-08,

DAC-08A, DAC-08C, and DAC-08H, respectively. For

single supply operation, refer to AN-1525.

Typical Application

Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package.

Figure 1. ±20 V

P-P

Output Digital-to-Analog Converter

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 DAC0800/DAC0802 8-Bit Digital-to-Analog Converters Check for Samples: DAC0800, DAC0802 FEATURES DESCRIPTION • • • • • • • The DAC0800 series are monolithic 8-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying DAC, monotonic performance over a 40 to 1 reference current range is possible.
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DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Absolute Maximum Ratings www.ti.com (1) Supply Voltage (V+ − V−) Power Dissipation ±18V or 36V (2) 500 mW Reference Input Differential Voltage V− to V+ (V14 to V15) Reference Input Common-Mode V− to V+ Range (V14, V15) Reference Input Current 5 mA − Logic Inputs − V to V plus 36V Analog Current Outputs (VS− = −15V) 4.25 mA (3) TBD V Storage Temperature −65°C to +150°C ESD Susceptibility Lead Temp.
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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Electrical Characteristics The following specifications apply for VS = ±15V, IREF = 2 mA and TMIN ≤ TA ≤ TMAX unless otherwise specified. Output characteristics refer to both IOUT and IOUT. Parameter Typ Max Min Typ Max Resolution 8 8 8 8 8 8 Monotonicity 8 8 8 8 8 8 Bits ±0.19 %FS ±0.
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DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com Connection Diagrams Figure 2. PDIP, CDIP Packages - Top View (See Package Number NFG0016E or NFE0016A) Figure 3. SOIC Package - Top View (See Package Number D0016A) Block Diagram Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 4.
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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Typical Performance Characteristics Full Scale Current vs. Reference Current LSB Propagation Delay vs. IFS Figure 5. Figure 6. Reference Input Frequency Response Reference Amp Common-Mode Range Curve 1: CC=15 pF, VIN=2 Vp-p centered at 1V. Curve 2: CC=15 pF, VIN=50 mVp-p centered at 200 mV. Curve 3: CC=0 pF, VIN=100 mVp-p centered at 0V and applied through 50Ω connected to pin 14.2V applied to R14. Figure 7. Note.
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DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Output Current vs. Output Voltage (Output Voltage Compliance) Output Voltage Compliance vs. Temperature Figure 11. Figure 12. Bit Transfer Characteristics Power Supply Current vs. +V Note. B1–B8 have identical transfer characteristics. Bits are fully switched with less than ½ LSB error, at less than ±100 mV from actual threshold.
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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 EQUIVALENT CIRCUIT Figure 17.
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DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. IO + IO = IFS for all logic states For fixed reference, TTL operation, typical values are: VREF = 10.000V RREF = 5.000k R15 ≈ RREF CC = 0.01 μF VLC = 0V (Ground) Figure 18. Basic Positive Reference Operation Figure 19. Recommended Full Scale Adjustment Circuit Figure 20.
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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 21. Basic Unipolar Negative Operation Table 1. Basic Unipolar Negative Operation B1 B2 B3 B4 B5 B6 B7 B8 IO mA IOmA EO EO Full Scale 1 1 1 1 1 1 1 1 1.992 0.000 −9.960 0.000 Full Scale−LSB 1 1 1 1 1 1 1 0 1.984 0.008 −9.920 −0.040 Half Scale+LSB 1 0 0 0 0 0 0 1 1.008 0.
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DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com (1) Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. (2) If RL = RL within ±0.05%, output is symmetrical about ground. Figure 23. Symmetrical Offset Binary Operation Table 3. Symmetrical Offset Binary Operation B1 B2 B3 B4 B5 B6 B7 B8 EO Pos. Full Scale 1 1 1 1 1 1 1 1 +9.960 Pos. Full Scale−LSB 1 1 1 1 1 1 1 0 +9.
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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Typical values: RIN=5k,+VIN=10V Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 26. Pulsed Reference Operation VTH = VLC + 1.4V 15V CMOS, HTL, HNIL VTH = 7.6V Note. Do not exceed negative logic input range of DAC. Figure 27.
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DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 29. Settling Time Measurement (1) For 1 μs conversion time with 8-bit resolution and 7-bit accuracy, an LM361 comparator replaces the LM319 and the reference current is doubled by reducing R1, R2 and R3 to 2.5 kΩ and R4 to 2 MΩ. (2) Pin numbers represent the PDIP package.
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DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision B (February 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC0800LCMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DAC0800LCMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DAC0802LCMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC0800LCMX SOIC D 16 2500 367.0 367.0 35.0 DAC0800LCMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 DAC0802LCMX SOIC D 16 2500 367.0 367.0 35.0 DAC0802LCMX/NOPB SOIC D 16 2500 367.0 367.0 35.
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MECHANICAL DATA NFG0016E N0016E N16E (Rev G) www.ti.
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